zl50415 Zarlink Semiconductor, zl50415 Datasheet - Page 65

• Manufacturer Part Number: zl50415
• Description: Managed 16-port 10/100 M + 2-port 1 G Ethernet Switch
• Manufacturer: Zarlink Semiconductor

14.4
14.4.1
I
Accessed by CPU, serial interface and I
14.4.2
I
Accessed by CPU, serial interface and I
14.4.3
I
Accessed by CPU, serial interface and I
In Port Based VLAN Mode
In Tag based VLAN Mode
2
2
2
C Address 036; CPU Address:h100
C Address 037; CPU Address:h101
C Address 038, CPU Address:h102
This register indicates the legal egress ports. A “1” on bit 7 means that the packet can be sent to port 7. A
“0” on bit 7 means that any packet destined to port 7 will be discarded. This register works with registers 1,
2 and 3 to form a 27 bit mask to all egress ports.
This is the default VLAN tag. It works with configuration register PVMAP00_1 [7:5] [3:0] to form a default
VLAN tag. If the received packet is untagged, then the packet is classified with the default VLAN tag. If the
received packet has a VLAN ID of 0, then PVID is used to replace the packet’s VLAN ID.
(Group 1 Address) VLAN Group
AVTCL – VLAN Type Code Register Low
AVTCH – VLAN Type Code Register High
PVMAP00_0 – Port 00 Configuration Register 0
Bit [5]:
Bit [6]:
Bit [7]:
Bit [7:0]:
Bit [7:0]:
Bit [7:0]:
Bit [7:0]:
•
•
•
VLAN Mask for ports 7 to 0 (Default FF)
PVID [7:0] (Default is FF)
GIGA port B use MII interface (10/100 M)
Reserved - Must be zero
GIGA port B direct flow control (MAC to MAC connection). ZL50418 supports
direct flow control mechanism; the flow control frame is therefore not sent
through the Gigabit port data path.
VLANType_LOW: Lower 8 bits of the VLAN type code (Default 00)
- 0: Gigabit port operates at 1000 mode (default)
- 1: Gigabit port operates at 10/100 mode
- 0: Direct flow control disabled (default)
- 1: Direct flow control enabled
VLANType_HIGH: Upper 8 bits of the VLAN type code (Default is 81)
2
2
2
C (R/W)
C (R/W)
C (R/W)
Zarlink Semiconductor Inc.
ZL50418
65
Data Sheet