zl50415 Zarlink Semiconductor, zl50415 Datasheet - Page 28

• Manufacturer Part Number: zl50415
• Description: Managed 16-port 10/100 M + 2-port 1 G Ethernet Switch
• Manufacturer: Zarlink Semiconductor

For example, in the above table a 1 denotes that an outgoing port is eligible to receive a packet from an incoming
port. A 0 (zero) denotes that an outgoing port is not eligible to receive a packet from an incoming port.
In this example:
•
•
•
5.8.1
The ZL50418 supports the IEEE 802.1q specification for “tagging” frames. The specification defines a way to
coordinate VLANs across multiple switches. In the specification, an additional 4-octet header (or “tag”) is inserted in
a frame after the source MAC address and before the frame type. 12 bits of the tag are used to define the VLAN ID.
Packets are then switched through the network with each ZL50418 simply swapping the incoming tag for an
appropriate forwarding tag rather than processing each packet's contents to determine the path. This approach
minimizes the processing needed once the packet enters the tag-switched network. In addition, coordinating VLAN
IDs across multiple switches enables VLANs to extend to multiple switches.
Up to 255 VLANs are supported in the ZL50418. The 4 K VLANs specified in the IEEE 802.1q are mapped to 255
VLAN indexes. The mapping is made by the VLAN index mapping table. Based on the VLAN index (VIXn), the
source and destination port membership is checked against the content in the VLAN Index Port association table. If
the destination port is a member of the VLAN, the packet is forwarded; otherwise it is discarded. If the source port is
not a member, a “New VLAN Port” message is sent to the CPU. A filter can be applied to discard the packet if the
source port is not a member of the VLAN.
5.9
The ZL50418 supports the following memory configurations. Pipeline SBRAM modes support
1 M and 2 M per bank configurations. For detail connection information, please reference the memory application
note.
Single Layer
(Bootstrap pin
TSTOUT13 = open)
Double Layer
(Bootstrap pin
TSTOUT13 = pull
down)
Data packets received at port #0 are eligible to be sent to outgoing ports 1 and 2.
Data packets received at port #1 are eligible to be sent to outgoing ports 0 and 2.
Data packets received at port #2 are NOT eligible to be sent to ports 0 and 1.
Configuration
Memory Configurations
Tag-Based VLAN
Table 5 - Supported Memory Configurations (Pipeline SBRAM Mode)
Two 128 K x 32
SRAM/bank
or
One 128 K x 64 SRAM/bank
NA
TSTOUT7 = open)
(Bootstrap pin
1 M per bank
Zarlink Semiconductor Inc.
ZL50418
28
Two 256 K x 32 SRAM/bank
Four 128 K x 32 SRAM/bank
or
Two 128 K x 64 SRAM/bank
TSTOUT7 = pull down)
(Bootstrap pin
2 M per bank
Connect 0E# and WE#
Connect 0E0# and WE0#
Connect 0E1# and WE1#
Connections
Data Sheet