zl50415 Zarlink Semiconductor, zl50415 Datasheet - Page 19

• Manufacturer Part Number: zl50415
• Description: Managed 16-port 10/100 M + 2-port 1 G Ethernet Switch
• Manufacturer: Zarlink Semiconductor

2.5.1
2.5.2
All registers in ZL50418 can be modified through this synchronous serial interface.
3.0
3.1
When a frame arrives, it is assigned a handle in memory by the Frame Control Buffer Manager (FCB Manager). An
FCB handle will always be available because of advance buffer reservations.
The memory (SRAM) interface is two 64-bit buses, connected to two SRAM banks, A and B. The Receive DMA
(RxDMA) is responsible for multiplexing the data and the address. On a port’s “turn,” the RxDMA will move 8 bytes
(or up to the end-of-frame) from the port’s associated RxFIFO into memory (Frame Data Buffer, or FDB).
Once an entire frame has been moved to the FDB and a good end-of-frame (EOF) has been received, the Rx
interface makes a switch request. The RxDMA arbitrates among multiple switch requests.
The switch request consists of the first 64 bytes of a frame, containing among other things, the source and
destination MAC addresses of the frame. The search engine places a switch response in the switch response
queue of the frame engine when done. Among other information the search engine will have resolved the
destination port of the frame and will have determined that the frame is unicast.
After processing the switch response, the Transmission Queue Manager (TxQ manager) of the frame engine is
responsible for notifying the destination port that it has a frame to forward to it. But first, the TxQ manager has to
decide whether or not to drop the frame, based on global FDB reservations and usage, as well as TxQ occupancy
Unicast Data Frame Forwarding
ZL50418 Data Forwarding Protocol
Write Command
Read Command
STROBE-
STROBE-
AUTOFD-
D0
D0
START
START
A0
A0 A1 A2
A1
A2
ADDRESS
ADDRESS
...
...
A9
A9
A10
A10
Figure 4 - Write Command
Figure 5 - Read Command
A11
Zarlink Semiconductor Inc.
COMMAND
A11
COMMAND
W
ZL50418
R
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
19
DATA
DATA
2 Extra clocks after last
transfer
Data Sheet