zl50415 Zarlink Semiconductor, zl50415 Datasheet - Page 110

• Manufacturer Part Number: zl50415
• Description: Managed 16-port 10/100 M + 2-port 1 G Ethernet Switch
• Manufacturer: Zarlink Semiconductor

When bit is 1:
Bit [0] – Flow control enable
Bit [1] – Full duplex port
Bit [2] – Fast Ethernet port (if not gigabit port)
Bit [3] – Link is down
Bit [4] – Giga port
Bit [5] – Signal detect (when PCS interface mode)
Bit [6] - Reserved
Bit [7] – Module detected (for hot swap purpose)
14.12.5
CPU Address: hF05
Accessed by serial interface (RW)
Bit [3] - Must be '1'
Bit [7] - Selects strap option or LCLK/OECLK registers
14.12.6
CPU Address: hF06
Accessed by serial interface (RW)
PD[12:10]
000b
001b
010b
011b
100b
101b
110b
111b
The LCLK delay from SCLK is the sum of the delay programmed in here and the delay in OECLK register.
0 - Strap option (default)
1 - LCLK/OECLK registers
PLLCR - PLL Control Register
LCLK - LA_CLK delay from internal OE_CLK
LCLK
01h
10h
02h
80h
40h
20h
08h
04h
Delay
1 Buffers Delay
5 Buffers Delay (Recommend)
2 Buffers Delay
8 Buffers Delay
7 Buffers Delay
6 Buffers Delay
4 Buffers Delay
3 Buffers Delay
Zarlink Semiconductor Inc.
ZL50418
110
Data Sheet