ADSP-BF533 AD [Analog Devices], ADSP-BF533 Datasheet - Page 13

• Manufacturer Part Number: ADSP-BF533
• Description: Blackfin Embedded Processor
• Manufacturer: AD [Analog Devices]

Alternatively, because the ADSP-BF531/2/3 processor includes
an on-chip oscillator circuit, an external crystal may be used.
The crystal should be connected across the CLKIN and XTAL
pins, with two capacitors connected as shown in
Capacitor values are dependent on crystal type and should be
specified by the crystal manufacturer. A parallel-resonant,
fundamental frequency, microprocessor-grade crystal should be
used.
As shown in
system peripheral clock (SCLK) are derived from the input
clock (CLKIN) signal. An on-chip PLL is capable of multiplying
the CLKIN signal by a user programmable 1x to 63x multiplica-
tion factor (bounded by specified minimum and maximum
VCO frequencies). The default multiplier is 10x, but it can be
modified by a software instruction sequence. On-the-fly fre-
quency changes can be effected by simply writing to the
PLL_DIV register.
All on-chip peripherals are clocked by the system clock (SCLK).
The system clock frequency is programmable by means of the
SSEL3–0 bits of the PLL_DIV register. The values programmed
CLKIN
REQUI RES PLL SEQUENCING
“FI NE” ADJUSTMENT
Figure 9 on Page
Figure 9. Frequency Modification Methods
0. 5 - 64
Figure 8. External Crystal Connections
PLL
CLKIN
SCLK
XTAL
SCLK CCLK
13, the core clock (CCLK) and
VCO
133 MHZ
CLKOUT
“COARSE” ADJUSTMENT
÷ 1, 2, 4, 8
÷ 1:15
ON-THE-FLY
Figure
Rev. 0 | Page 13 of 56 | March 2004
CCLK
SCLK
8.
ADSP-BF531/ADSP-BF532/ADSP-BF533
into the SSEL fields define a divide ratio between the PLL output
(VCO) and the system clock. SCLK divider values are 1 through
15.
Table 6. Example System Clock Ratios
The maximum frequency of the system clock is f
the divisor ratio must be chosen to limit the system clock fre-
quency to its maximum of f
dynamically without any PLL lock latencies by writing the
appropriate values to the PLL divisor register (PLL_DIV).
The core clock (CCLK) frequency can also be dynamically
changed by means of the CSEL1–0 bits of the PLL_DIV register.
Supported CCLK divider ratios are 1, 2, 4, and 8, as shown in
Table
fast core frequency modifications.
Table 7. Core Clock Ratios
BOOTING MODES
The ADSP-BF531/2/3 processor has two mechanisms (listed in
Table
ory after a reset. A third mode is provided to execute from
external memory, bypassing the boot sequence.
Table 8. Booting Modes
Signal Name
SSEL3–0
0001
0011
1010
Signal Name
CSEL1–0
00
01
10
11
BMODE1–0
00
01
10
11
Table 6
7. This programmable core clock capability is useful for
8) for automatically loading internal L1 instruction mem-
illustrates typical system clock ratios.
Divider Ratio
VCO/SCLK
1:1
3:1
10:1
Divider Ratio
VCO/CCLK
1:1
2:1
4:1
8:1
Description
Execute from 16-Bit External Memory (Bypass
Boot ROM)
Boot from 8-Bit or 16-Bit FLASH
Reserved
Boot from SPI Serial EEPROM (8-, 16-, or 24-Bit
address range)
SCLK
. The SSEL value can be changed
Example Frequency Ratios
(MHz)
VCO
100
400
500
Example Frequency Ratios
VCO
300
300
500
200
SCLK
SCLK
CCLK
300
150
125
25
100
133
50
. Note that