ADSP-BF533 AD [Analog Devices], ADSP-BF533 Datasheet - Page 22

• Manufacturer Part Number: ADSP-BF533
• Description: Blackfin Embedded Processor
• Manufacturer: AD [Analog Devices]

ADSP-BF531/ADSP-BF532/ADSP-BF533
Clock and Reset Timing
Table 15
Absolute Maximum Ratings on Page
CLKIN and clock multipliers must not select core/peripheral
clocks in excess of 600/133 MHz.
Table 15. Clock and Reset Timing
1
2
Parameter
Timing Requirements
t
t
t
t
Applies to bypass mode and non-bypass mode.
Applies after power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 2000 CLKIN cycles, while RESET is asserted,
CKIN
CKINL
CKINH
WRST
assuming stable power supplies and CLKIN (not including start-up time of external clock oscillator).
and
Figure 10
CLKIN
RESET
CLKIN Period
CLKIN Low Pulse
CLKIN High Pulse
RESET Asserted Pulse Width Low
describe clock and reset operations. Per
t
CKINL
t
CKIN
1
1
20, combinations of
t
CKINH
Rev. 0 | Page 22 of 56 | March 2004
2
Figure 10. Clock and Reset Timing
t
WRST
Min
25.0
10.0
10.0
11 t
CKIN
Max
100.0
Unit
ns
ns
ns
ns