ADSP-BF533 AD [Analog Devices], ADSP-BF533 Datasheet - Page 7

• Manufacturer Part Number: ADSP-BF533
• Description: Blackfin Embedded Processor
• Manufacturer: AD [Analog Devices]

Table 2. Core Event Controller (CEC)
interrupt events by writing the appropriate values into the Inter-
rupt Assignment Registers (IAR).
into the SIC and the default mappings into the CEC.
Event Control
The ADSP-BF531/2/3 processor provides the user with a very
flexible mechanism to control the processing of events. In the
CEC, three registers are used to coordinate and control events.
Each register is 16 bits wide:
Priority
(0 is Highest)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
• CEC Interrupt Latch Register (ILAT) – The ILAT register
• CEC Interrupt Mask Register (IMASK) – The IMASK reg-
• CEC Interrupt Pending Register (IPEND) – The IPEND
indicates when events have been latched. The appropriate
bit is set when the processor has latched the event and
cleared when the event has been accepted into the system.
This register is updated automatically by the controller, but
it may be written only when its corresponding IMASK bit
is cleared.
ister controls the masking and unmasking of individual
events. When a bit is set in the IMASK register, that event is
unmasked and will be processed by the CEC when asserted.
A cleared bit in the IMASK register masks the event, pre-
venting the processor from servicing the event even though
the event may be latched in the ILAT register. This register
may be read or written while in supervisor mode. (Note
that general-purpose interrupts can be globally enabled and
disabled with the STI and CLI instructions, respectively.)
register keeps track of all nested events. A set bit in the
IPEND register indicates the event is currently active or
nested at some level. This register is updated automatically
by the controller but may be read while in supervisor mode.
Event Class
Emulation/Test Control
Reset
Non-Maskable Interrupt NMI
Exception
Reserved
Hardware Error
Core Timer
General Interrupt 7
General Interrupt 8
General Interrupt 9
General Interrupt 10
General Interrupt 11
General Interrupt 12
General Interrupt 13
General Interrupt 14
General Interrupt 15
Table 3
describes the inputs
EVT Entry
EMU
RST
EVX
IVHW
IVTMR
IVG7
IVG8
IVG9
IVG10
IVG11
IVG12
IVG13
IVG14
IVG15
Rev. 0 | Page 7 of 56 | March 2004
ADSP-BF531/ADSP-BF532/ADSP-BF533
Table 3. System Interrupt Controller (SIC)
The SIC allows further control of event processing by providing
three 32-bit interrupt control and status registers. Each register
contains a bit corresponding to each of the peripheral interrupt
events shown in
Peripheral Interrupt Event
PLL Wakeup
DMA Error
PPI Error
SPORT 0 Error
SPORT 1 Error
SPI Error
UART Error
Real-Time Clock
DMA Channel 0 (PPI)
DMA Channel 1 (SPORT 0 RX)
DMA Channel 2 (SPORT 0 TX)
DMA Channel 3 (SPORT 1 RX)
DMA Channel 4 (SPORT 1 TX)
DMA Channel 5 (SPI)
DMA Channel 6 (UART RX)
DMA Channel 7 (UART TX)
Timer 0
Timer 1
Timer 2
PF Interrupt A
PF Interrupt B
DMA Channels 8 and 9
(Memory DMA Stream 1)
DMA Channels 10 and 11
(Memory DMA Stream 0)
Software Watchdog Timer
• SIC Interrupt Mask Register (SIC_IMASK)– This register
• SIC Interrupt Status Register (SIC_ISR) – As multiple
• SIC Interrupt Wakeup Enable Register (SIC_IWR) – By
controls the masking and unmasking of each peripheral
interrupt event. When a bit is set in the register, that
peripheral event is unmasked and will be processed by the
system when asserted. A cleared bit in the register masks
the peripheral event, preventing the processor from servic-
ing the event.
peripherals can be mapped to a single event, this register
allows the software to determine which peripheral event
source triggered the interrupt. A set bit indicates the
peripheral is asserting the interrupt, and a cleared bit indi-
cates the peripheral is not asserting the event.
enabling the corresponding bit in this register, a peripheral
can be configured to wake up the processor, should the
core be idled when the event is generated.
mation, see Dynamic Power Management on Page
Table 3 on Page
7.
Default Mapping
IVG7
IVG7
IVG7
IVG7
IVG7
IVG7
IVG7
IVG8
IVG8
IVG9
IVG9
IVG9
IVG9
IVG10
IVG10
IVG10
IVG11
IVG11
IVG11
IVG12
IVG12
IVG13
IVG13
IVG13
(For more infor-
11.)