ADSP-BF533 AD [Analog Devices], ADSP-BF533 Datasheet - Page 9

• Manufacturer Part Number: ADSP-BF533
• Description: Blackfin Embedded Processor
• Manufacturer: AD [Analog Devices]

WATCHDOG TIMER
The ADSP-BF531/2/3 processor includes a 32-bit timer that can
be used to implement a software watchdog function. A software
watchdog can improve system availability by forcing the proces-
sor to a known state through generation of a hardware reset,
non-maskable interrupt (NMI), or general-purpose interrupt, if
the timer expires before being reset by software. The program-
mer initializes the count value of the timer, enables the
appropriate interrupt, then enables the timer. Thereafter, the
software must reload the counter before it counts to zero from
the programmed value. This protects the system from remain-
ing in an unknown state where software, which would normally
reset the timer, has stopped running due to an external noise
condition or software error.
If configured to generate a hardware reset, the watchdog timer
resets both the core and the ADSP-BF531/2/3 processor periph-
erals. After a reset, software can determine if the watchdog was
the source of the hardware reset by interrogating a status bit in
the watchdog timer control register.
The timer is clocked by the system clock (SCLK), at a maximum
frequency of f
TIMERS
There are four general-purpose programmable timer units in
the ADSP-BF531/2/3 processor. Three timers have an external
pin that can be configured either as a Pulse-Width Modulator
(PWM) or timer output, as an input to clock the timer, or as a
mechanism for measuring pulse-widths and periods of external
events. These timers can be synchronized to an external clock
input to the PF1 pin, an external clock input to the PPI_CLK
pin, or to the internal SCLK.
The timer units can be used in conjunction with the UART to
measure the width of the pulses in the data stream to provide an
auto-baud detect function for a serial channel.
The timers can generate interrupts to the processor core provid-
ing periodic events for synchronization, either to the system
clock or to a count of external signals.
In addition to the three general-purpose programmable timers,
a fourth timer is also provided. This extra timer is clocked by the
internal processor clock and is typically used as a system tick
clock for generation of operating system periodic interrupts.
SERIAL PORTS (SPORTS)
The ADSP-BF531/2/3 processor incorporates two dual-channel
synchronous serial ports (SPORT0 and SPORT1) for serial and
multiprocessor communications. The SPORTs support the fol-
lowing features:
• I
• Bidirectional operation – Each SPORT has two sets of inde-
• Buffered (8-deep) transmit and receive ports – Each port
pendent transmit and receive pins, enabling eight channels
of I
has a data register for transferring data words to and from
other processor components and shift registers for shifting
data in and out of the data registers.
2
S capable operation.
2
S stereo audio.
SCLK
.
Rev. 0 | Page 9 of 56 | March 2004
ADSP-BF531/ADSP-BF532/ADSP-BF533
SERIAL PERIPHERAL INTERFACE (SPI) PORT
The ADSP-BF531/2/3 processor has an SPI-compatible port
that enables the processor to communicate with multiple SPI-
compatible devices.
The SPI interface uses three pins for transferring data: two data
pins (Master Output-Slave Input, MOSI, and Master Input-
Slave Output, MISO) and a clock pin (Serial Clock, SCK). An
SPI chip select input pin (SPISS) lets other SPI devices select the
processor, and seven SPI chip select output pins (SPISEL7–1) let
the processor select other SPI devices. The SPI select pins are
reconfigured Programmable Flag pins. Using these pins, the SPI
port provides a full-duplex, synchronous serial interface, which
supports both master/slave modes and multimaster
environments.
The SPI port’s baud rate and clock phase/polarities are pro-
grammable, and it has an integrated DMA controller,
configurable to support transmit or receive data streams. The
SPI’s DMA controller can only service unidirectional accesses at
any given time.
The SPI port’s clock rate is calculated as:
Where the 16-bit SPI_Baud register contains a value of 2 to
65,535.
• Clocking – Each transmit and receive port can either use an
• Word length – Each SPORT supports serial data words
• Framing – Each transmit and receive port can run with or
• Companding in hardware – Each SPORT can perform
• DMA operations with single-cycle overhead – Each SPORT
• Interrupts – Each transmit and receive port generates an
• Multichannel capability – Each SPORT supports 128 chan-
external serial clock or generate its own, in frequencies
ranging from (f
from 3 to 32 bits in length, transferred most-significant-bit
first or least-significant-bit first.
without frame sync signals for each data word. Frame sync
signals can be generated internally or externally, active high
or low, and with either of two pulse widths and early or late
frame sync.
A-law or µ-law companding according to ITU recommen-
dation G.711. Companding can be selected on the transmit
and/or receive channel of the SPORT without additional
latencies.
can automatically receive and transmit multiple buffers of
memory data. The processor can link or chain sequences of
DMA transfers between a SPORT and memory.
interrupt upon completing the transfer of a data-word or
after transferring an entire data buffer or buffers through
DMA.
nels out of a 1024-channel window and is compatible with
the H.100, H.110, MVIP-90, and HMVIP standards.
SPI Clock Rate
SCLK
/131,070) Hz to (f
=
-------------------------------- -
2
SPI_Baud
f
SCLK
SCLK
/2) Hz.