ADSP-BF533 AD [Analog Devices], ADSP-BF533 Datasheet - Page 37

• Manufacturer Part Number: ADSP-BF533
• Description: Blackfin Embedded Processor
• Manufacturer: AD [Analog Devices]

Timer Cycle Timing
Table 30
input signal is asynchronous in “width capture mode” and
“external clock mode” and has an absolute maximum input fre-
quency of f
Table 30. Timer Cycle Timing
1
2
Parameter
Timing Characteristics
t
t
Switching Characteristics
t
The minimum pulse widths apply for TMRx input pins in width capture and external clock modes. They also apply to the PF1 or PPI_CLK input pins in PWM output mode.
The minimum time for t
WL
WH
HTO
CLKOUT
(PWM OUTPUT MODE)
EXTERNAL CLOCK MODES)
and
(WIDTH CAPTURE AND
SCLK
Figure 23
TMRx
/2 MHz.
TMRx
Timer Pulse Width Input Low
Timer Pulse Width Input High
Timer Pulse Width Output
HTO
describe timer expired operations. The
is one cycle, and the maximum time for t
2
(Measured in SCLK Cycles)
1
1
(Measured in SCLK Cycles)
(Measured in SCLK Cycles)
Figure 23. Timer PWM_OUT Cycle Timing
Rev. 0 | Page 37 of 56 | March 2004
t
WL
HTO
equals (2
32
–1) cycles.
ADSP-BF531/ADSP-BF532/ADSP-BF533
t
WH
t
HTO
Min
1
1
1
Max
(2
32
–1)
Unit
SCLK
SCLK
SCLK