ADSP-BF533 AD [Analog Devices], ADSP-BF533 Datasheet - Page 6

• Manufacturer Part Number: ADSP-BF533
• Description: Blackfin Embedded Processor
• Manufacturer: AD [Analog Devices]

ADSP-BF531/ADSP-BF532/ADSP-BF533
The asynchronous memory controller can be programmed to
control up to four banks of devices with very flexible timing
parameters for a wide variety of devices. Each bank occupies a
1M byte segment regardless of the size of the devices used, so
that these banks will only be contiguous if each is fully popu-
lated with 1M byte of memory.
I/O Memory Space
Blackfin processors do not define a separate I/O space. All
resources are mapped through the flat 32-bit address space.
On-chip I/O devices have their control registers mapped into
memory-mapped registers (MMRs) at addresses near the top of
the 4G byte address space. These are separated into two smaller
blocks, one of which contains the control MMRs for all core
functions, and the other of which contains the registers needed
for setup and control of the on-chip peripherals outside of the
core. The MMRs are accessible only in supervisor mode and
appear as reserved space to on-chip peripherals.
Booting
The ADSP-BF531/2/3 processor contains a small boot kernel,
which configures the appropriate peripheral for booting. If the
ADSP-BF531/2/3 processor is configured to boot from boot
ROM memory space, the processor starts executing from the
on-chip boot ROM. For more information, see
on Page
0xFFA0 C000
0xFFFF FFFF
0xFFE0 0000
0xFFC0 0000
0xFFB0 1000
0xFFB0 0000
0xFFA1 4000
0xFFA1 0000
0xFFA0 8000
0xFFA0 0000
0xFF90 8000
0xFF90 4000
0xFF80 8000
0xFF80 4000
0xEF00 0000
0x2040 0000
0x2030 0000
0x2020 0000
0x2010 0000
0x2000 0000
0x0800 0000
0x0000 0000
13.
Figure 5. ADSP-BF531 Internal/External Memory Map
RESERVED
RESERVED
SCRATCHPAD SRAM (4K BYTE)
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
ASYNC MEMORY BANK 3 (1M BYTE)
ASYNC MEMORY BANK 2 (1M BYTE)
ASYNC MEMORY BANK 1 (1M BYTE)
ASYNC MEMORY BANK 0 (1M BYTE)
RESERVED
SDRAM MEMORY (16M BYTE TO 128M BYTE)
CORE MMR REGISTERS (2M BYTE)
SYSTEM MMR REGISTERS (2M BYTE)
INSTRUCTION SRAM / CACHE (16K BYTE)
INSTRUCTION SRAM (16K BYTE)
DATA BANK A SRAM / CACHE (16K BYTE)
Booting Modes
Rev. 0 | Page 6 of 56 | March 2004
Event Handling
The event controller on the ADSP-BF531/2/3 processor handles
all asynchronous and synchronous events to the processor. The
ADSP-BF531/2/3 processor provides event handling that sup-
ports both nesting and prioritization. Nesting allows multiple
event service routines to be active simultaneously. Prioritization
ensures that servicing of a higher priority event takes prece-
dence over servicing of a lower priority event. The controller
provides support for five different types of events:
Each event type has an associated register to hold the return
address and an associated return-from-event instruction. When
an event is triggered, the state of the processor is saved on the
supervisor stack.
The ADSP-BF531/2/3 processor Event Controller consists of
two stages, the Core Event Controller (CEC) and the System
Interrupt Controller (SIC). The Core Event Controller works
with the System Interrupt Controller to prioritize and control all
system events. Conceptually, interrupts from the peripherals
enter into the SIC, and are then routed directly into the general-
purpose interrupts of the CEC.
Core Event Controller (CEC)
The CEC supports nine general-purpose interrupts (IVG15–7),
in addition to the dedicated interrupt and exception events. Of
these general-purpose interrupts, the two lowest-priority inter-
rupts (IVG15–14) are recommended to be reserved for software
interrupt handlers, leaving seven prioritized interrupt inputs to
support the peripherals of the ADSP-BF531/2/3 processor.
Table 2
in the Event Vector Table (EVT), and lists their priorities.
System Interrupt Controller (SIC)
The System Interrupt Controller provides the mapping and
routing of events from the many peripheral interrupt sources to
the prioritized general-purpose interrupt inputs of the CEC.
Although the ADSP-BF531/2/3 processor provides a default
mapping, the user can alter the mappings and priorities of
• Emulation – An emulation event causes the processor to
• Reset – This event resets the processor.
• Non-Maskable Interrupt (NMI) – The NMI event can be
• Exceptions – Events that occur synchronously to program
• Interrupts – Events that occur asynchronously to program
enter emulation mode, allowing command and control of
the processor via the JTAG interface.
generated by the software watchdog timer or by the NMI
input signal to the processor. The NMI event is frequently
used as a power-down indicator to initiate an orderly shut-
down of the system.
flow (i.e., the exception will be taken before the instruction
is allowed to complete). Conditions such as data alignment
violations and undefined instructions cause exceptions.
flow. They are caused by input pins, timers, and other
peripherals, as well as by an explicit software instruction.
describes the inputs to the CEC, identifies their names