ADSP-BF533 AD [Analog Devices], ADSP-BF533 Datasheet - Page 21

• Manufacturer Part Number: ADSP-BF533
• Description: Blackfin Embedded Processor
• Manufacturer: AD [Analog Devices]

TIMING SPECIFICATIONS
Table 10
the ADSP-BF531/2/3 processor clocks. Take care in selecting
MSEL, SSEL, and CSEL ratios so as not to exceed the maximum
core clock and system clock as described in
Table 10. Core and System Clock Requirements—ADSP-BF533SKBC600
Table 11. Core and System Clock Requirements—ADSP-BF533SBBC500 and ADSP-BF533SBBZ500
Table 12. Core and System Clock Requirements—ADSP-BF532/531 All Package Types
Table 13. Phase-Locked Loop Operating Conditions
Table 14. Maximum SCLK Conditions
1
Parameter
t
t
t
t
t
t
Parameter
t
t
t
t
t
t
Parameter
t
t
t
t
t
t
Parameter
f
Parameter
MBGA
f
f
LQFP
f
f
Set bit 7 (output delay) of PLL_CTL register.
VCO
SCLK
SCLK
SCLK
SCLK
CCLK
CCLK
CCLK
CCLK
CCLK
SCLK
CCLK
CCLK
CCLK
CCLK
CCLK
SCLK
CCLK
CCLK
CCLK
CCLK
CCLK
SCLK
Core Cycle Period (V
Core Cycle Period (V
Core Cycle Period (V
Core Cycle Period (V
Core Cycle Period (V
System Clock Period
through
Core Cycle Period (V
Core Cycle Period (V
Core Cycle Period (V
Core Cycle Period (V
Core Cycle Period (V
System Clock Period
Core Cycle Period (V
Core Cycle Period (V
Core Cycle Period (V
Core Cycle Period (V
Core Cycle Period (V
System Clock Period
Voltage Controlled Oscillator (VCO) Frequency
Condition
V
V
V
V
DDINT
DDINT
DDINT
DDINT
Table 14
1.14 V
1.14 V
1.14 V
1.14 V
describe the timing requirements for
DDINT
DDINT
DDINT
DDINT
DDINT
DDINT
DDINT
DDINT
DDINT
DDINT
DDINT
DDINT
DDINT
DDINT
DDINT
=1.2 V–5%)
=1.1 V–5%)
=1.0 V–5%)
=0.9 V–5%)
=0.8 V)
=1.2 V–5%)
=1.1 V–5%)
=1.0 V–5%)
=0.9 V–5%)
=0.8 V)
=1.2 V–5%)
=1.1 V–5%)
=1.0 V–5%)
=0.9 V–5%)
=0.8 V)
Absolute Maximum
Rev. 0 | Page 21 of 56 | March 2004
Min
2.5
2.75
3.00
3.25
4.0
Maximum of 7.5 or t
Min
1.67
2.10
2.35
2.66
4.00
Maximum of 7.5 or t
Min
2.0
2.25
2.50
3.00
4.00
Maximum of 7.5 or t
Min
50
V
133
100
133
83
ADSP-BF531/ADSP-BF532/ADSP-BF533
DDEXT
Ratings on Page
(VCO) operating frequencies described in
describes Phase-Locked Loop operating conditions.
= 3.3 V
20, and the Voltage Controlled Oscillator
CCLK
CCLK
CCLK
Max
Max CCLK
V
133
100
133
83
DDEXT
1
1
Max
= 2.5 V
Max
Max
Table
13.
Table 13
Unit
ns
ns
ns
ns
ns
ns
Unit
ns
ns
ns
ns
ns
ns
Unit
ns
ns
ns
ns
ns
ns
Unit
MHz
Unit
MHz
MHz
MHz
MHz