ADSP-BF533 AD [Analog Devices], ADSP-BF533 Datasheet - Page 42

• Manufacturer Part Number: ADSP-BF533
• Description: Blackfin Embedded Processor
• Manufacturer: AD [Analog Devices]

ADSP-BF531/ADSP-BF532/ADSP-BF533
TEST CONDITIONS
All timing parameters appearing in this data sheet were mea-
sured under the conditions described in this section.
Output Enable Time
Output pins are considered to be enabled when they have made
a transition from a high impedance state to the point when they
start driving. The output enable time t
the point when a reference signal reaches a high or low voltage
level to the point when the output starts driving as shown in the
Output Enable/Disable diagram
t
switches to when the output voltage reaches 2.0 V (output high)
or 1.0 V (output low). Time t
output starts driving to when the output reaches the 1.0 V or
2.0 V trip voltage. Time t
equation:
If multiple pins (such as the data bus) are enabled, the measure-
ment value is that of the first pin to start driving.
Output Disable Time
Output pins are considered to be disabled when they stop driv-
ing, go into a high impedance state, and start to decay from their
output high or low voltage. The time for the voltage on the bus
to decay by V is dependent on the capacitive load, C
load current, I
equation:
The output disable time t
t
t
switches to when the output voltage decays V from the mea-
sured output high or output low voltage. The time t
calculated with test loads C
Example System Hold Time Calculation
To determine the data output hold time in a particular system,
first calculate t
sor’s output voltage and the input threshold for the device
requiring the hold time. A typical V will be 0.4 V. C
total bus capacitance (per data line), and I
three-state current (per data line). The hold time will be t
plus the minimum disable time (for example, t
SDRAM write cycle).
Capacitive Loading
Output delays and holds are based on standard capacitive loads:
30 pF on all pins (see
Page 44
ENA_MEASURED
DIS_MEASURED
DIS_MEASURED
V to be the difference between the ADSP-BF531/2/3 proces-
show how output rise time varies with capacitance. The
L
DECAY
and t
is the interval from when the reference signal
. This decay time can be approximated by the
is the interval from when the reference signal
t
ENA
DECAY
t
Figure
using the equation given above. Choose
DECAY
=
ENA
DIS
t
as shown in
ENA_MEASURED
L
34).
=
is the difference between
and I
TRIP
is calculated as shown in the
C
(Figure
Figure 36
is the interval from when the
L
L
, and with V equal to 0.5 V.
V
ENA
Figure
–
33). The time
I
t
L
L
TRIP
through
is the interval from
is the total leakage or
33. The time
DSDAT
Figure 43 on
Rev. 0 | Page 42 of 56 | March 2004
DECAY
L
for an
L
is the
and the
DECAY
is
delay and hold specifications given should be derated by a factor
derived from these figures. The graphs in these figures may not
be linear outside the ranges shown.
(MEASURED)
(MEASURED)
t
DIS
V
V
OUTPUT
OH
OL
Figure 34. Equivalent Device Loading for AC Measurements
(Includes All Fixtures)
OUTPUT
OUTPUT STOPS DRIVING
PIN
TO
INPUT
OR
Measurements (Except Output Enable/Disable)
Figure 35. Voltage Reference Levels for AC
1.5V
Figure 33. Output Enable/Disable
REFERENCE
t
V
V
DIS_MEASURED
OH
OL
SIGNAL
t
(MEASURED)
DECAY
VOLTAGE TO BE APPROXIMATELY 1.5V.
(MEASURED) + V
TEST CONDITIONS CAUSE THIS
HIGH IMPEDANCE STATE.
30pF
t
ENA
V
50 OHMS
OUTPUT STARTS DRIVING
t
2.0V
1.0V
ENA-MEASURED
t
TRIP
(MEASURED)
(MEASURED)
1.5V
V
V
1.5V
OL
OH