ADSP-BF533 AD [Analog Devices], ADSP-BF533 Datasheet - Page 28

• Manufacturer Part Number: ADSP-BF533
• Description: Blackfin Embedded Processor
• Manufacturer: AD [Analog Devices]

ADSP-BF531/ADSP-BF532/ADSP-BF533
Serial Ports
Table 21
through
Table 21. Serial Ports—External Clock
1
Table 22. Serial Ports—Internal Clock
1
Table 23. Serial Ports—External Clock
1
Table 24. Serial Ports—Internal Clock
1
Parameter
Timing Requirements
t
t
t
t
t
t
Parameter
Timing Requirements
t
t
t
t
t
t
Parameter
Switching Characteristics
t
t
t
t
Parameter
Switching Characteristics
t
t
t
t
t
Referenced to sample edge.
Referenced to sample edge.
Referenced to drive edge.
Referenced to drive edge.
SFSE
HFSE
SDRE
HDRE
SCLKEW
SCLKE
SFSI
HFSI
SDRI
HDRI
SCLKEW
SCLKE
DFSE
HOFSE
DDTE
HDTE
DFS
HOFS
DDT
HDT
SCLKIW
I
I
I
I
Figure 18 on Page 32
through
Table 26 on Page 29
TFS/RFS Setup Before TSCLK/RSCLK
TFS/RFS Hold After TSCLK/RSCLK
Receive Data Setup Before RSCLK
Receive Data Hold After RSCLK
TSCLK/RSCLK Width
TSCLK/RSCLK Period
TFS/RFS Setup Before TSCLK/RSCLK
TFS/RFS Hold After TSCLK/RSCLK
Receive Data Setup Before RSCLK
Receive Data Hold After RSCLK
TSCLK/RSCLK Width
TSCLK/RSCLK Period
TFS/RFS Delay After TSCLK/RSCLK (Internally Generated TFS/RFS)
TFS/RFS Hold After TSCLK/RSCLK (Internally Generated TFS/RFS)
Transmit Data Delay After TSCLK
Transmit Data Hold After TSCLK
TFS/RFS Delay After TSCLK/RSCLK (Internally Generated TFS/RFS)
TFS/RFS Hold After TSCLK/RSCLK (Internally Generated TFS/RFS)
Transmit Data Delay After TSCLK
Transmit Data Hold After TSCLK
TSCLK/RSCLK Width
describe Serial Port operations.
and
Figure 16 on Page 30
1
1
1
1
1
1
Rev. 0 | Page 28 of 56 | March 2004
1
1
1
1
1
1
1
1
1
1
Min
3.0
3.0
3.0
3.0
4.5
15.0
Min
8.0
–2.0
6.0
0.0
4.5
15.0
Min
0.0
0.0
Min
4.5
1.0
2.0
Max
Max
Max
10.0
10.0
Max
3.0
3.0
Unit
ns
ns
ns
ns
ns
ns
Unit
ns
ns
ns
ns
ns
ns
Unit
ns
ns
ns
ns
Unit
ns
ns
ns
ns
ns