EZ80F91MCU ZILOG [Zilog, Inc.], EZ80F91MCU Datasheet - Page 203

• Manufacturer Part Number: EZ80F91MCU
• Description: eZ80Acclaim-TM Flash Microcontrollers
• Manufacturer: ZILOG [Zilog, Inc.]

UART Functional Description
PS019209-0504
UART Functions
The UART Baud Rate Generator creates the clock for the serial transmit and
receive functions. The UART module supports all of the various options in the
asynchronous transmission and reception protocol including:
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The UART contains 16-byte-deep FIFOs in each direction. The FIFOs can be
enabled or disabled by the application. The receive FIFO features trigger-level
detection logic, which enables the CPU to block-transfer data bytes from the
receive FIFO.
The UART function implements:
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UART Transmitter
The transmitter block controls the data transmitted on the TxD output. It imple-
ments the FIFO, access via the UARTx_THR register, the transmit shift register,
the parity generator, and control logic for the transmitter to control parameters for
the asynchronous communications protocol.
The UARTx_THR is a Write Only register. The CPU writes the data byte to be
transmitted into this register. In FIFO mode, up to 16 data bytes can be written via
the UARTx_THR register. The data byte from the FIFO is transferred to the trans-
mit shift register at the appropriate time and transmitted via TxD output. After
SYNC_RESET, the UARTx_THR register is empty. Therefore, the Transmit Hold-
ing Register Empty (THRE) bit (bit 5 of the
is sent to the CPU if interrupts are enabled. The CPU can reset this interrupt by
loading data into the UARTx_THR register, which clears the transmitter interrupt.
The transmit shift register places the byte to be transmitted on the TxD signal seri-
ally. The least-significant bit of the byte to be transmitted is shifted out first and the
most-significant bit is shifted out last. The control logic within the block adds the
asynchronous communications protocol bits to the data byte being transmitted.
5- to 9-bit transmit/receive
Start bit generation and detection
Parity generation and detection
Stop bit generation and detection
Break generation and detection
The transmitter and associated control logic
The receiver and associated control logic
The modem interface and associated logic
P R E L I M I N A R Y
UARTx_LSR
Universal Asynchronous Receiver/Transmitter
register) is 1. An interrupt
Product Specification
eZ80F91 MCU
184