EZ80F91MCU ZILOG [Zilog, Inc.], EZ80F91MCU Datasheet - Page 242

• Manufacturer Part Number: EZ80F91MCU
• Description: eZ80Acclaim-TM Flash Microcontrollers
• Manufacturer: ZILOG [Zilog, Inc.]

PS019209-0504
Figure 46. Clock Synchronization In I
Arbitration
Any master can initiate a transfer if the bus is free. As a result, multiple masters
can each generate a START condition if the bus is free within a minimum period. If
multiple masters generate a START condition, a START is defined for the bus.
However, arbitration defines which MASTER controls the bus. Arbitration takes
place on the SDA line. As mentioned, START conditions are initiated only while
the SCL line is held High. If, during this period, a master (M1) initiates a High-to-
Low transition—i.e., a START condition—while a second master (M2) transmits a
Low signal on the line, then the first master, M1, cannot take control of the bus. As
a result, the data output stage for M1 is disabled.
Arbitration can continue for many bits. Its first stage is comparison of the address
bits. If the masters are each trying to address the same device, arbitration contin-
ues with a comparison of the data. Because address and data information on the
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that loses the arbitration can generate clock pulses until the end of the byte in
which it loses the arbitration.
If a master also incorporates a slave function and it loses arbitration during the
addressing stage, it is possible that the winning master is trying to address it. The
losing master must switch over immediately to its slave receiver mode. Figure 46
illustrates the arbitration procedure for two masters. Of course, more can be
involved, depending on how many masters are connected to the bus. The
moment there is a difference between the internal data level of the master gener-
ating DATA 1 and the actual level on the SDA line, its data output is switched off,
which means that a High output level is then connected to the bus. As a result, the
data transfer initiated by the winning master is not affected. Because control of the
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there is no central master, nor any order of priority on the bus.
CLK1 Signal
CLK2 Signal
2
2
SCL Signal
C bus is used for arbitration, no information is lost during this process. A master
C bus is decided solely on the address and data sent by competing masters,
State
Wait
Counter
P R E L I M I N A R Y
Reset
2
Start Counting
C Protocol
High Period
Product Specification
I
2
C Serial I/O Interface
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