EZ80F91MCU ZILOG [Zilog, Inc.], EZ80F91MCU Datasheet - Page 33

• Manufacturer Part Number: EZ80F91MCU
• Description: eZ80Acclaim-TM Flash Microcontrollers
• Manufacturer: ZILOG [Zilog, Inc.]

Table 2. Pin Identification on the eZ80F91 Device (Continued)
PS019209-0504
LQFP
Pin #
50
51
52
53
54
55
Note: *PHY represents the physical layer of the OSI model.
BGA
Pin#
L5
K5
J5
M6
L6
K6
Symbol
MREQ
RD
WR
INSTRD
WAIT
RESET
Function
Memory
Request
Read
Write
Instruction
Read Indicator
WAIT Request Schmitt-trigger input,
Reset
P R E L I M I N A R Y
Signal Direction
Bidirectional, Active
Low
Output, Active Low
Output, Active Low
Output, Active Low
Active Low
Schmitt-trigger input,
Active Low
Description
MREQ Low indicates that the
CPU is accessing a location in
memory. The RD, WR, and
INSTRD signals indicate the type
of access. The eZ80F91 device
does not drive this line during
RESET. It is an input in bus
acknowledge cycles.
RD Low indicates that the
eZ80F91 device is reading from
the current address location. This
pin is tristated during bus
acknowledge cycles.
WR indicates that the CPU is
writing to the current address
location. This pin is tristated
during bus acknowledge cycles.
INSTRD (with MREQ and RD)
indicates the eZ80F91 device is
fetching an instruction from
memory. This pin is tristated
during bus acknowledge cycles.
Driving the WAIT pin Low forces
the CPU to wait additional clock
cycles for an external peripheral
or external memory to complete
its Read or Write operation.
This signal is used to initialize the
eZ80F91 device. This input must
be Low for a minimum of 3
system clock cycles, and must be
held Low until the clock is stable.
This input includes a Schmitt
trigger to allow RC rise times.
Product Specification
Architectural Overview
eZ80F91 MCU
14