EZ80F91MCU ZILOG [Zilog, Inc.], EZ80F91MCU Datasheet - Page 25

• Manufacturer Part Number: EZ80F91MCU
• Description: eZ80Acclaim-TM Flash Microcontrollers
• Manufacturer: ZILOG [Zilog, Inc.]

Table 2. Pin Identification on the eZ80F91 Device
PS019209-0504
LQFP
Pin #
1
2
3
4
Note: *PHY represents the physical layer of the OSI model.
Pin Characteristics
BGA
Pin#
A1
B1
B2
C3
Table 2 describes the pins and functions of the eZ80F91 MCU’s 144-pin LQFP
package and 144-ball BGA package.
Symbol
ADDR0
ADDR1
ADDR2
ADDR3
Function
Address Bus
Address Bus
Address Bus
Address Bus
P R E L I M I N A R Y
Signal Direction
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Description
Configured as an output in
normal operation. The address
bus selects a location in memory
or I/O space to be read or written.
Configured as an input during bus
acknowledge cycles. Drives the
Chip Select/Wait State Generator
block to generate Chip Selects.
Configured as an output in
normal operation. The address
bus selects a location in memory
or I/O space to be read or written.
Configured as an input during bus
acknowledge cycles. Drives the
Chip Select/Wait State Generator
block to generate Chip Selects.
Configured as an output in
normal operation. The address
bus selects a location in memory
or I/O space to be read or written.
Configured as an input during bus
acknowledge cycles. Drives the
Chip Select/Wait State Generator
block to generate Chip Selects.
Configured as an output in
normal operation. The address
bus selects a location in memory
or I/O space to be read or written.
Configured as an input during bus
acknowledge cycles. Drives the
Chip Select/Wait State Generator
block to generate Chip Selects.
Product Specification
Architectural Overview
eZ80F91 MCU
6