EZ80F91MCU ZILOG [Zilog, Inc.], EZ80F91MCU Datasheet - Page 239

• Manufacturer Part Number: EZ80F91MCU
• Description: eZ80Acclaim-TM Flash Microcontrollers
• Manufacturer: ZILOG [Zilog, Inc.]

PS019209-0504
Data Validity
The data on the SDA line must be stable during the High period of the clock. The
High or Low state of the data line can only change when the clock signal on the
SCL line is Low, as illustrated in Figure 42.
Figure 42. I
START and STOP Conditions
Within the I
and STOP conditions. Figure 43 illustrates a High-to-Low transition on the SDA
line while SCL is High, indicating a START condition. A Low-to-High transition on
the SDA line while SCL is High defines a STOP condition.
START and STOP conditions are always generated by the master. The bus is
considered to be busy after a START condition. The bus is considered to be free
for a defined time after a STOP condition.
Figure 43. START and STOP Conditions In I
SDA Signal
SCL Signal
SDA Signal
SCL Signal
2
2
C Clock and Data Relationship
C bus protocol, unique situations arise which are defined as START
START Condition
S
Data Valid
Data Line
Stable
P R E L I M I N A R Y
Data Allowed
Change of
2
C Protocol
Product Specification
STOP Condition
I
2
C Serial I/O Interface
eZ80F91 MCU
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