EZ80F91MCU ZILOG [Zilog, Inc.], EZ80F91MCU Datasheet - Page 230

• Manufacturer Part Number: EZ80F91MCU
• Description: eZ80Acclaim-TM Flash Microcontrollers
• Manufacturer: ZILOG [Zilog, Inc.]

Figure 41. SPI Timing
PS019209-0504
(CPHA bit = 0) Data Out
(CPHA bit = 1) Data Out
ENABLE (To Slave)
SCK (CPOL bit = 0)
SCK (CPOL bit = 1)
Sample Input
Sample Input
exchanging a byte of data during a sequence of eight clock cycles. Because SCK
is generated by the master, the SCK pin becomes an input on a slave device. The
SPI contains an internal divide-by-two clock divider. In MASTER mode, the SPI
serial clock is one-half the frequency of the clock signal created by the SPI’s Baud
Rate Generator.
As demonstrated in Figure 41 and Table 111, four possible timing relations can be
chosen by using the clock polarity (CPOL) and CPHA control bits in the SPI Con-
trol register. See the
ter and slave must operate with the identical timing, CPOL, and CPHA. The
master device always places data on the MOSI line a half-cycle before the clock
edge (SCK signal), for the slave device to latch the data.
Table 111. SPI Clock Phase and Clock Polarity Operation
CPHA
0
0
CPOL
MSB
0
1
MSB
1
SPI Control Register
6
P R E L I M I N A R Y
Transmit
Falling
Rising
6
Edge
2
SCK
Number of Cycles on the SCK Signal
5
5
3
4
Receive
Falling
Rising
Edge
4
SCK
4
(SPI_CTL) on page 216. Both the mas-
3
3
5
2
State
SCK
High
Low
Idle
2
6
Product Specification
1
Serial Peripheral Interface
1
7
Characters?
LSB
eZ80F91 MCU
Between
SS High
LSB
Yes
Yes
8
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