EZ80F91MCU ZILOG [Zilog, Inc.], EZ80F91MCU Datasheet - Page 337

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EZ80F91MCU

Manufacturer Part Number
EZ80F91MCU
Description
eZ80Acclaim-TM Flash Microcontrollers
Manufacturer
ZILOG [Zilog, Inc.]
Datasheet
Table 204. Pin to Boundary Scan Cell Mapping (Continued)
PS019209-0504
Pin
A1
A0
A0
A0
WP
MII_MDIO
MII_MDIO
MII_MDIO
MII_MDC
MII_RxD3
MII_RxD2
MII_RxD1
MII_RxD0
MII_Rx_DV
MII_Rx_CLK
MII_Rx_ER
MII_Tx_ER
MII_Tx_CLK
MII_Tx_EN
MII_TxD0
MII_TxD1
Notes:
1. The address bits 0–7, 8–15, and 16–23 each share a single output enable. In this table, the output enables are
2. Direction on the data bus is controlled by a single output enable. It is shown in this table as being associated
3. MREQ,
shown to be associated with the least-significant bit that they control.
with D[0].
IORQ
, INSTRDN, RD, and WR share an output enable; it is associated in this table with WR.
Direction
Output
Output
Output
Output
Output
Output
Output
Output
Input
OEN
Input
Input
OEN
Input
Input
Input
Input
Input
Input
Input
Input
Scan Cell #
100
101
102
103
104
105
106
86
87
88
89
90
91
92
93
94
95
96
97
98
99
P R E L I M I N A R Y
Pin
PD6
PD6
PD5
PD5
PD5
PD4
PD4
PD4
PD3
PD3
PD3
PD2
PD2
PD2
PD1
PD1
PD1
PD0
PD0
PD0
Direction
Output
Output
Output
Output
Output
Output
Output
Product Specification
OEN
Input
OEN
Input
OEN
Input
OEN
Input
OEN
Input
OEN
Input
OEN
On-Chip Instrumentation
eZ80F91 MCU
Scan Cell #
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
318

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