EZ80F91MCU ZILOG [Zilog, Inc.], EZ80F91MCU Datasheet - Page 300

• Manufacturer Part Number: EZ80F91MCU
• Description: eZ80Acclaim-TM Flash Microcontrollers
• Manufacturer: ZILOG [Zilog, Inc.]

PS019209-0504
EMAC Receive Write Pointer Register—High Byte
Because of the size of the EMAC’s 8 KB SRAM, the upper three bits of the EMAC
Receive Write Pointer Register are always zero.
Table 177. EMAC Receive Write Pointer Register—High Byte
(EMAC_RWP_H = 0052h)
EMAC Transmit Read Pointer Register—Low Byte
The Low byte of the Transmit Read Pointer register reports the current TxDMA
Transmit Read pointer.This pointer is initialized to EmacTLBP whenever
Emac_RST bits SRST or HRRTN are set. Because the size of the packet is lim-
ited to a minimum of 32 bytes, the last five bits are always zero. See Table 178.
Table 178. EMAC Transmit Read Pointer Register—Low Byte
(EMAC_TRP_L = 0053h)
Bit
Reset
CPU Access
Note: R = Read Only.
Bit
Position
[7:0]
EMAC_RWP_H
Bit
Reset
CPU Access
Note: R = Read Only.
Bit
Position
[7:0]
EMAC_TRP_L
Value
00h–
E0h
Value
00h–
1Fh
Description
These bits represent the Low byte of the 2-byte EMAC
TxDMA
EMAC_TRP_L}. Bit 7 is bit 7 of the 16-bit value. Bit 0 is bit 0
(lsb) of the 16-bit value.
P R E L I M I N A R Y
R
R
7
0
7
0
Description
These bits represent the High byte of the 2-byte EMAC
RxDMA Receive Write Pointer value, {EMAC_RWP_H,
EMAC_RWP_L}. Bit 7 is bit 15 (msb) of the 16-bit value. Bit
0 is bit 8 of the 16-bit value.
R
R
6
0
6
0
Transmit Read Pointer
R
R
5
0
5
0
R
R
4
0
4
0
Ethernet Media Access Controller
R
R
3
0
3
0
value, {EMAC_TRP_H,
Product Specification
R
R
2
0
2
0
eZ80F91 MCU
R
R
1
0
1
0
R
R
0
0
0
0
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