EZ80F91MCU ZILOG [Zilog, Inc.], EZ80F91MCU Datasheet - Page 79

• Manufacturer Part Number: EZ80F91MCU
• Description: eZ80Acclaim-TM Flash Microcontrollers
• Manufacturer: ZILOG [Zilog, Inc.]

PS019209-0504
Note:
supply ground. Writing a 1 to the Port x Data register outputs a High at the pin.
Writing a 0 to the Port x Data register results in a high-impedance output.
GPIO Mode 5.
GPIO Mode 6.
and a falling edge on the pin cause an interrupt request to be sent to the CPU.
Writing a 1 to the Port x Data register bit position resets the corresponding inter-
rupt request. Writing a 0 produces no effect. The programmer must set the Port x
Data register before entering the edge-triggered interrupt mode.
GPIO Mode 7.
to the alternate (secondary) functions assigned to the pin. For example, the alter-
nate mode function for PC7 is RI1 and the alternate mode function for PB4 is the
Timer 4 output. When GPIO Mode 7 is enabled, the pin output data and pin
tristated control come from the alternate function's data output and tristate control,
respectively. The value in the Port x Data register produces no effect on operation.
Input signals are sampled by the system clock before being passed to the alter-
nate function input.
Alternate function inputs are routed to the associated functional block regardless
of the GPIO mode setting.
Px_DDR does not indicate the GPIO direction in all alternate function modes.
GPIO Mode 8.
interrupt request is generated when the level at the pin is the same as the level
stored in the Port x Data register. The port pin value is sampled by the system
clock. The input pin must be held at the selected interrupt level for a minimum of 2
clock periods to initiate an interrupt. The interrupt request remains active as long
as this condition is maintained at the external source.
GPIO Mode 9.
The value in the Port x Data register determines if a positive or negative edge
causes an interrupt request. Writing a 0 to the Port x Data register bit sets the
selected pin to generate an interrupt request for falling edges. Writing a 1 to the
Port x Data register bit sets the selected pin to generate an interrupt request for
rising edges. Any time a port pin is configured for an edge-trigger interrupt, writing
a 1 to the Port x Data register causes a reset of the edge-trigger interrupt. Writing
a 0 produces no effect on operation. The programmer must set the Port x Data
register before entering the single- or dual-edge-triggered interrupt mode.
A simplified block diagram of a GPIO port pin is illustrated in Figure 5.
Reserved. This pin produces high-impedance output.
This bit enables a dual edge-triggered interrupt mode. Both a rising
For Ports B, C, and D, the port pin is configured to pass control over
The port pin is configured for level-sensitive interrupt modes. An
The port pin is configured for single edge-triggered interrupt mode.
P R E L I M I N A R Y
General-Purpose Input/Output
Product Specification
eZ80F91 MCU
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