HD6433308 HITACHI [Hitachi Semiconductor], HD6433308 Datasheet - Page 196

• Manufacturer Part Number: HD6433308
• Description: Hitachi Single-Chip MicroComputer
• Manufacturer: HITACHI [Hitachi Semiconductor]

The TDR is initialized to H’FF at a reset and in the standby modes.
9.2.5 Serial Mode Register (SMR) – H’FFD8
Bit
Initial value
Read/Write
The SMR is an 8-bit readable/writable register that controls the communication format and selects
the clock rate for the internal clock source. It is initialized to H’04 at a reset and in the standby
modes.
Bit 7 – Communication Mode (C/A): This bit selects the asynchronous or synchronous
communication mode.
Bit 7
C/A
Bit 6 – Character Length (CHR): This bit selects the character length in asynchronous mode. It
is ignored in synchronous mode.
Bit 6
CHR Description
Bit 5 – Parity Enable (PE): This bit selects whether to add a parity bit in asynchronous mode. It
is ignored in synchronous mode.
Bit 5
PE
0
1
0
1
0
1
8 Bits per character.
7 Bits per character.
Description
Transmit: No parity bit is added.
Receive: Parity is not checked.
Transmit: A parity bit is added.
Receive: Parity is checked.
Description
Asynchronous communication.
Clock-synchronized communication.
R/W
C/A
7
0
CHR
R/W
6
0
R/W
PE
5
0
183
R/W
O/E
4
0
STOP
R/W
3
0
—
—
2
1
CKS1
R/W
1
0
(Initial value)
(Initial value)
(Initial value)
CKS0
R/W
0
0