HD6433308 HITACHI [Hitachi Semiconductor], HD6433308 Datasheet - Page 207

• Manufacturer Part Number: HD6433308
• Description: Hitachi Single-Chip MicroComputer
• Manufacturer: HITACHI [Hitachi Semiconductor]

Transmitting and receiving operations in the two modes are described next.
9.3.2 Asynchronous Mode
In asynchronous mode, each character is individually synchronized by framing it with a start bit
and stop bit.
Full duplex data transfer is possible because the SCI has independent transmit and receive sections.
Double buffering in both sections enables the SCI to be programmed for continuous data transfer.
Figure 9-2 shows the general format of one character sent or received in the asynchronous mode.
The communication channel is normally held in the mark state (High). Character transmission or
reception starts with a transition to the space state (Low).
The first bit transmitted or received is the start bit (Low). It is followed by the data bits, in which
the least significant bit (LSB) comes first. The data bits are followed by the parity bit, if present,
then the stop bit or bits (High) confirming the end of the frame.
In receiving, the SCI synchronizes on the falling edge of the start bit, and samples each bit at the
center of the bit (at the 8th cycle of the internal serial clock, which runs at 16 times the bit rate).
Idle state
Start bit
D0
D1
Dn
Parity bit
Stop bit
0 or 1 bit
1 or 2 bits
1 bit
7 or 8 bits
One character
Figure 9-2. Data Format in Asynchronous Mode
(1) Data Format: Table 9-7 lists the data formats that can be sent and received in asynchronous
mode. Eight formats can be selected by bits in the SMR.
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