HD6433308 HITACHI [Hitachi Semiconductor], HD6433308 Datasheet - Page 85

• Manufacturer Part Number: HD6433308
• Description: Hitachi Single-Chip MicroComputer
• Manufacturer: HITACHI [Hitachi Semiconductor]

Bits 0 to 7 – IRQ
the IRQ
Bit i
IRQiSC
Edge-sensed interrupt signals are latched (if enabled) until the interrupt is serviced. They are
latched even if the interrupt mask bit (I) is set in the CCR, and remain latched even if the enable bit
(IRQ
(3) IRQ Enable Register (IER)—H’FFC7
Bit
Initial value
Read/Write
Bits 0 to 7 – IRQ
signals individually.
After a reset, all IRQi interrupts are disabled (as well as masked).
Bit i
IRQiE
4.2.2 External Interrupts
The external interrupts are NMI and IRQ
(1) NMI: A nonmaskable interrupt is generated on the rising or falling edge of the NMI input
signal regardless of whether the I (interrupt mask) bit is set in the CCR. The valid edge is selected
by the NMIEG bit in the system control register.
An NMI has highest priority and is always accepted as soon as the current instruction ends, unless
the current instruction is an ANDC, ORC, XORC, or LDC instruction. When an NMI interrupt is
0
1
0
1
0
E to IRQ
0
to IRQ
Description
IRQi is level-sensed.
IRQi is sensed on the falling edge.
Description
IRQi is disabled.
IRQi is enabled.
7
E) is later cleared to 0.
7
IRQ
0
0
inputs are edge-sensed or level-sensed.
R/W
to IRQ
to IRQ
7
0
7
E
7
7
IRQ
R/W
Sense Control (IRQ
Enable (IRQ
6
0
6
E
IRQ
R/W
5
0
0
5
0
E
to IRQ
E to IRQ
IRQ
R/W
70
0
7
4
0
SC to IRQ
.
4
E
7
E): These bits enable or disable the IRQi
IRQ
R/W
3
0
7
3
SC): These bits determine whether
E
IRQ
R/W
2
0
2
E
(Initial state)
(Initial state)
IRQ
R/W
1
0
1
E
IRQ
R/W
0
0
0
E