ATMEGA48V_11 ATMEL [ATMEL Corporation], ATMEGA48V_11 Datasheet - Page 102

• Manufacturer Part Number: ATMEGA48V_11
• Description: 8-bit Atmel Microcontroller with 4/8/16K Bytes In-System Programmable Flash
• Manufacturer: ATMEL [ATMEL Corporation]

2545T–AVR–05/11
Table 15-4
rect PWM mode.
Table 15-4.
Note:
• Bits 5:4 – COM0B1:0: Compare match output B mode
These bits control the Output Compare pin (OC0B) behavior. If one or both of the COM0B1:0
bits are set, the OC0B output overrides the normal port functionality of the I/O pin it is connected
to. However, note that the Data Direction Register (DDR) bit corresponding to the OC0B pin
must be set in order to enable the output driver.
When OC0B is connected to the pin, the function of the COM0B1:0 bits depends on the
WGM02:0 bit setting.
are set to a normal or CTC mode (non-PWM).
Table 15-5.
Table 15-6
mode.
Table 15-6.
COM0A1
COM0B1
COM0B1
0
0
1
1
0
0
1
1
0
0
1
1
1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the Com-
pare Match is ignored, but the set or clear is done at TOP. See
page 123
shows the COM0A1:0 bit functionality when the WGM02:0 bits are set to phase cor-
shows the COM0B1:0 bit functionality when the WGM02:0 bits are set to fast PWM
Compare output mode, phase correct PWM mode
Compare output mode, non-PWM mode.
Compare output mode, fast PWM mode
COM0A0
COM0B0
COM0B0
for more details.
0
1
0
1
0
1
0
1
0
1
0
1
Table 15-5
Description
Normal port operation, OC0A disconnected
WGM02 = 0: Normal Port Operation, OC0A Disconnected
WGM02 = 1: Toggle OC0A on Compare Match
Clear OC0A on Compare Match when up-counting
Set OC0A on Compare Match when down-counting
Set OC0A on Compare Match when up-counting
Clear OC0A on Compare Match when down-counting
Description
Normal port operation, OC0B disconnected
Toggle OC0B on compare match
Clear OC0B on compare match
Set OC0B on compare match
Description
Normal port operation, OC0B disconnected
Reserved
Clear OC0B on compare match, set OC0B at BOTTOM,
(non-inverting mode)
Set OC0B on compare match, clear OC0B at BOTTOM,
(inverting mode)
shows the COM0B1:0 bit functionality when the WGM02:0 bits
(1)
.
ATmega48/88/168
(1)
.
“Phase correct PWM mode” on
102