ATMEGA48V_11 ATMEL [ATMEL Corporation], ATMEGA48V_11 Datasheet - Page 53
ATMEGA48V_11
Manufacturer Part Number
ATMEGA48V_11
Description
8-bit Atmel Microcontroller with 4/8/16K Bytes In-System Programmable Flash
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
1.ATMEGA48V_11.pdf
(377 pages)
- Current page: 53 of 377
- Download datasheet (9Mb)
11.9
11.9.1
11.9.2
2545T–AVR–05/11
Register description
MCUSR – MCU status register
WDTCSR – Watchdog timer control register
The MCU status register provides information on which reset source caused an MCU reset.
• Bit 7..4: Res: Reserved bits
These bits are unused bits in the Atmel ATmega48/88/168, and will always read as zero.
• Bit 3 – WDRF: Watchdog system reset flag
This bit is set if a watchdog system reset occurs. The bit is reset by a power-on reset, or by writ-
ing a logic zero to the flag.
• Bit 2 – BORF: Brown-out reset flag
This bit is set if a brown-out reset occurs. The bit is reset by a power-on reset, or by writing a
logic zero to the flag.
• Bit 1 – EXTRF: External reset flag
This bit is set if an external reset occurs. The bit is reset by a power-on reset, or by writing a logic
zero to the flag.
• Bit 0 – PORF: Power-on reset flag
This bit is set if a power-on reset occurs. The bit is reset only by writing a logic zero to the flag.
To make use of the reset flags to identify a reset condition, the user should read and then reset
the MCUSR as early as possible in the program. If the register is cleared before another reset
occurs, the source of the reset can be found by examining the reset flags.
• Bit 7 - WDIF: Watchdog interrupt flag
This bit is set when a time-out occurs in the watchdog timer and the watchdog timer is config-
ured for interrupt. WDIF is cleared by hardware when executing the corresponding interrupt
handling vector. Alternatively, WDIF is cleared by writing a logic one to the flag. When the I-bit in
SREG and WDIE are set, the Watchdog time-out interrupt is executed.
• Bit 6 - WDIE: Watchdog interrupt enable
When this bit is written to one and the I-bit in the status register is set, the watchdog interrupt is
enabled. If WDE is cleared in combination with this setting, the watchdog timer is in interrupt
mode, and the corresponding interrupt is executed if time-out in the watchdog timer occurs.
Bit
0x35 (0x55)
Read/write
Initial value
Bit
(0x60)
Read/write
Initial value
WDIF
R/W
7
0
R
7
–
0
WDIE
R/W
6
0
R
6
–
0
WDP3
R/W
5
0
R
5
–
0
WDCE
R/W
4
0
R
4
–
0
WDE
WDRF
R/W
R/W
3
X
3
WDP2
R/W
BORF
See Bit Description
ATmega48/88/168
R/W
2
0
2
WDP1
R/W
EXTRF
R/W
1
0
1
WDP0
R/W
PORF
0
0
R/W
0
WDTCSR
MCUSR
53
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