ATMEGA48V_11 ATMEL [ATMEL Corporation], ATMEGA48V_11 Datasheet - Page 187

• Manufacturer Part Number: ATMEGA48V_11
• Description: 8-bit Atmel Microcontroller with 4/8/16K Bytes In-System Programmable Flash
• Manufacturer: ATMEL [ATMEL Corporation]

20.8.3
2545T–AVR–05/11
Asynchronous operational range
Figure 20-7. Stop bit sampling and next start bit sampling.
The same majority voting is done to the stop bit as done for the other bits in the frame. If the stop
bit is registered to have a logic 0 value, the Frame Error (FEn) Flag will be set.
A new high to low transition indicating the start bit of a new frame can come right after the last of
the bits used for majority voting. For Normal Speed mode, the first low level sample can be at
point marked (A) in
(B). (C) marks a stop bit of full length. The early start bit detection influences the operational
range of the Receiver.
The operational range of the Receiver is dependent on the mismatch between the received bit
rate and the internally generated baud rate. If the Transmitter is sending frames at too fast or too
slow bit rates, or the internally generated baud rate of the Receiver does not have a similar (see
Table 20-2 on page
frames to the start bit.
The following equations can be used to calculate the ratio of the incoming data rate and internal
receiver baud rate.
D
S
S
S
R
Table 20-2 on page 188
that can be tolerated. Note that Normal Speed mode has higher toleration of baud rate
variations.
F
M
slow
(U2X = 0)
(U2X = 1)
Sample
Sample
RxD
R
slow
Sum of character size and parity size (D = 5 to 10 bit)
Samples per bit. S = 16 for Normal Speed mode and S = 8 for Double Speed
mode.
First sample number used for majority voting. S
for Double Speed mode.
Middle sample number used for majority voting. S
S
is the ratio of the slowest incoming data rate that can be accepted in relation to the
receiver baud rate. R
accepted in relation to the receiver baud rate.
M
=
= 5 for Double Speed mode.
Figure
------------------------------------------ -
S 1
188) base frequency, the Receiver will not be able to synchronize the
–
1
1
(
and
D
+
2
20-7. For Double Speed mode the first low level must be delayed to
+
D S ⋅
1
Table 20-3 on page 188
)S
3
2
+
S
4
F
fast
5
3
is the ratio of the fastest incoming data rate that can be
6
7
4
8
STOP 1
9
5
list the maximum receiver baud rate error
10
0/1
(A)
6
R
0/1
F
ATmega48/88/168
fast
= 8 for normal speed and S
M
0/1
0/1
(B)
= 9 for normal speed and
=
-----------------------------------
(
D
(
+
D
1
+
)S
2
)S
+
(C)
S
M
F
187
= 4