HD6417021 Hitachi Semiconductor, HD6417021 Datasheet - Page 124

• Manufacturer Part Number: HD6417021
• Description: SuperH RISC engine
• Manufacturer: Hitachi Semiconductor

Bit 7: RFSHE
0
1
•
Bit 6: RMODE
0
1
•
Bit 5: RLW1
0
1
•
8.2.7
The refresh timer control/status register (RTCSR) is a 16-bit read/write register that selects the
clock input to refresh timer counter (RTCNT) and controls compare match interrupts (CMI). It is
initialized to H'0000 by a power-on reset, but is not initialized by a manual reset or by the standby
mode.
To prevent RTCSR from being written incorrectly, it must be written by a different method from
most other registers. A word transfer operation is used, H'A5 is written in the top byte and the
actual data is written in the lower byte. For details, see section 8.2.11, Notes on Register Access.
108 HITACHI
Bit 6 (refresh mode (RMODE)): When DRAM refresh control is selected (RFSHE = 1),
RMODE selects whether to perform CAS-before-RAS (CBR) refresh or self-refresh. When
this bit is cleared to 0, a CBR refresh is performed at the cycle set in the refresh timer
control/status register (RTCSR) and refresh time constant register (RTCOR). When set to 1, it
the DRAM does a self-refresh. When refresh control is not selected (RFSHE = 0), the RMODE
bit setting is not valid. When canceling self-refresh, set RMODE to 0 with RFSHE set to 1.
Bits 5 and 4—Insert wait states during CBR refresh bits 1 and 0 (RLW1, RLW0): These bits
select the number of wait states to be inserted (1–4) during CAS-before-RAS refresh. When
CBR refresh is performed and the RW1 bit of WCR1 is set to 1, the number of wait states
selected in the RLW1 and RLW0 is inserted regardless of the WAIT signal. When the RW1 bit
is cleared to 0, the RLW1 and RLW0 bit settings are ignored and no wait states are inserted.
Bits 3–0 (reserved): These bits always read as 0. The write value should always be 0.
Refresh Timer Control/Status Register (RTCSR)
Bit 4: RLW0
0
1
0
1
Description
Refresh control disabled. RTCNT can be used as an 8-bit interval
timer. (initial value)
Refresh control enabled
Description
CAS-before-RAS refresh (initial value)
Self-refresh
Description
Inserts 1 state (initial value)
Inserts 2 states
Inserts 3 states
Inserts 4 states