HD6417021 Hitachi Semiconductor, HD6417021 Datasheet - Page 71

• Manufacturer Part Number: HD6417021
• Description: SuperH RISC engine
• Manufacturer: Hitachi Semiconductor

Table 4.5
Type
Instruction fetch CPU
Data read/write
Note: See section 8, Bus State Controller, for details on the on-chip peripheral module space.
4.3.2
When an address error occurs, address error exception processing starts after both the bus cycle
that caused the address error and the instructions that were being executed at that time have been
completed. The CPU then:
1. Pushes the SR onto the stack.
2. Pushes the program counter onto the stack. The PC value saved is the top address of the
3. Fetches the exception service routine start address from the exception vector table for the
instruction following the last instruction to be executed.
address error that occurred and starts program execution from that address. The branch that
occurs here is not a delayed branch.
Address Error Exception Processing
Bus Cycle
Address Error Sources
Bus Master
CPU or DMAC
Operation
Instruction fetch from even address
Instruction fetch from odd address
Instruction fetch from outside on-chip
peripheral module space
Instruction fetch from on-chip peripheral
module space
Access to word data from even address
Access to word data from odd address
Access to long word data aligned on long
word boundary
Access to long word data not aligned on
long word boundary
Access to word or byte data in on-chip
peripheral module space*
Access to long word data in 16-bit on-chip
peripheral module space*
Access to long word data in 8-bit on-chip
peripheral module space*
Address Error
None (normal)
Address error
None (normal)
Address error
None (normal)
Address error
None (normal)
Address error
None (normal)
None (normal)
Address error
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