RG82845M Intel, RG82845M Datasheet - Page 120

no-image

RG82845M

Manufacturer Part Number
RG82845M
Description
Chipset Memory Controller Hub Mobile
Manufacturer
Intel
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
RG82845MP
Manufacturer:
INTEL
Quantity:
3
Part Number:
RG82845MP SL66J
Manufacturer:
INTEL
Quantity:
1 440
Part Number:
RG82845MP/SL66J
Manufacturer:
inte
Quantity:
1
Part Number:
RG82845MPES
Manufacturer:
INTEL
Quantity:
8
Part Number:
RG82845MPSL66J
Manufacturer:
RFMD
Quantity:
1 831
Part Number:
RG82845MZ SL64T
Manufacturer:
INTEL
Quantity:
20 000
Part Number:
RG82845MZ
Manufacturer:
INTEL
Quantity:
3 600
Intel
5.3.6.
5.3.6.1.
120
Table 30. Fast Write Initialization
Table 31. PCI Commands Supported by the MCH-M When Acting as a FRAME# Target
®
82845MP/82845MZ Chipset-Mobile (MCH-M)
Memory writes originating from the host or from the hub interface use the Fast Write protocol when it is
both capability enabled and enabled. The data rate used to perform the Fast Writes is dependent on the
bits set in the AGP Command Register bits 2:0 (DATA_RATE). If bit 2 of the
AGPCMD[DATA_RATE] field is 1, the data transfers occur using 4x strobing. If bit 1 of
AGPCMD[DATA_RATE] field is 1, the data transfers occur using 2x strobing. If bit 0 of
AGPCMD[DATA_RATE] field is 1, Fast Writes are disabled and data transfers occur using standard
PCI protocol. Note that only one of the three DATA_RATE bits may be set by initialization software.
This is summarized in the following table.
AGP FRAME# Transactions on AGP
The MCH-M accepts and generates AGP FRAME# transactions on the AGP bus. The MCH-M
guarantees that AGP FRAME# accesses to DRAM are kept coherent with the processor caches by
generating snoops to the host bus. LOCK#, SERR#, and PERR# signals are not supported.
MCH-M Target and Initiator Operations for AGP FRAME# Transactions
The following table summarizes MCH-M target operation for AGP FRAME# initiators. The only cycles
that will be claimed are memory accesses to main memory.
Interrupt Acknowledge
Special Cycle
I/O Read
I/O Write
Reserved
Reserved
Memory Read
Memory Write
Reserved
FWEN
PCI Command
0
1
1
1
DATA_RATE
[2]
X
0
0
1
C/BE[3:0]# Encoding
DATA_RATE
0000
0001
0010
0011
0110
0110
0111
0111
1000
0100
0101
[1]
Datasheet
0
1
0
x
DATA_RATE
[0]
x
1
0
0
Cycle Destination
The Hub interface
The Hub interface
Main Memory
Main Memory
N/A
N/A
N/A
N/A
N/A
N/A
N/A
MCH-M =>AGP Master Write
MCH-M
2x Strobing
4x Strobing
Protocol
Response as aFRAME#
1x
1x
No Response
No Response
No Response
No Response
No Response
No Response
No Response
No Response
No Response
Post Data
Target
Read
250687-002
R

Related parts for RG82845M