RG82845M Intel, RG82845M Datasheet - Page 52

• Manufacturer Part Number: RG82845M
• Description: Chipset Memory Controller Hub Mobile
• Manufacturer: Intel

Intel
3.7.3.
52
®
82845MP/82845MZ Chipset-Mobile (MCH-M)
Address Offset:
PCICMD – PCI Command Register – Device #0
Default:
Access:
Size
Since MCH-M Device #0 does not physically reside on PCI0 many of the bits are not implemented
15:10
Bit
9
8
7
6
5
4
3
2
1
0
Reserved
Fast Back-to-Back Enable (RO). This bit controls whether or not the master can do fast back-to-
back writes to different targets. Since device #0 is strictly a target this bit is not implemented and is
hardwired to 0. Writes to this bit position have no effect.
SERR Enable (SERRE) (R/W). This bit is a global enable bit for Device #0 SERR messaging. The
MCH-M does not have an SERR# signal. The MCH-M communicates the SERR# condition by
sending an SERR message to the ICH3-M. If this bit is set to a 1, the MCH-M is enabled to generate
SERR messages over hub interface for specific Device #0 error conditions that are individually
enabled in the ERRCMD register. The error status is reported in the ERRSTS and PCISTS registers.
If SERRE is reset to 0, then the SERR message is not generated by the MCH-M for Device #0.
NOTE: This bit only controls SERR message for the Device #0. Device 1 has its own SERRE bits to
control error reporting for error conditions occurring on their respective devices.
Address/Data Stepping (RO). Address/data stepping is not implemented in the MCH-M, and this bit
is hardwired to 0. Writes to this bit position have no effect.
Parity Error Enable (PERRE) (R/W). PERR# is not implemented by the MCH-M, and this bit is
hardwired to 0. Writes to this bit position have no effect.
VGA Palette Snoop (RO). The MCH-M does not implement this bit and it is hardwired to a 0. Writes
to this bit position have no effect.
Memory Write and Invalidate Enable(MWIE) (RO). The MCH-M does not implement this bit and it
is hardwired to a 0. Writes to this bit position have no effect.
Special Cycle Enable(SCE) (RO). The MCH-M does not implement this bit and it is hardwired to a
0. Writes to this bit position have no effect.
Bus Master Enable (BME) (RO). The MCH-M is always enabled as a master on hub interface A.
This bit is hardwired to a “1”. Writes to this bit position have no effect.
Memory Access Enable (MAE) (RO). The MCH-M always allows access to main memory. This bit
is not implemented and is hardwired to 1. Writes to this bit position have no effect.
I/O Access Enable (IOAE) (RO). This bit is not implemented in the MCH-M and is hardwired to a 0.
Writes to this bit position have no effect.
04-05h
0006h
Read/Write, Read Only
16 bits
Datasheet
Descriptions
250687-002
.
R