RG82845M Intel, RG82845M Datasheet - Page 78

• Manufacturer Part Number: RG82845M
• Description: Chipset Memory Controller Hub Mobile
• Manufacturer: Intel

Intel
3.7.32.
78
®
82845MP/82845MZ Chipset-Mobile (MCH-M)
#0
Address Offset:
LPTT – AGP Low Priority Transaction Timer Register – Device
Default Value:
Access:
Size:
LPTT is an 8-bit register similar in a function to AMTT. This register is used to control the minimum
tenure on the AGP for low priority data transaction (both reads and writes) issued using PIPE# or SBA
mechanisms.
The number of clocks programmed in the LPTT represents the guaranteed time slice (measured in 66
MHz clocks) allotted to the current low priority AGP transaction data transfer state. This does not
necessarily apply to a single transaction, but can span multiple low-priority transactions of the same type.
After this time expires the AGP arbiter may grant the bus to another agent if there is a pending request.
The LPTT does not apply in the case of high-priority request where ownership is transferred directly to
high-priority requesting queue. The default value of LPTT is 00h and disables this function. The LPTT
value can be programmed with 8-clock granularity. For example, if the LPTT is programmed to 10h,
then the selected value corresponds to the time period of 16 AGP (66 MHz) clocks.
7:3
2:0
Bit
Low Priority Transaction Timer Count Value (LPTTC): The number of clocks programmed in these
bits represents the guaranteed time slice (measured in eight 66-MHz clock granularity) allotted to the
current low priority AGP transaction data transfer state.
Reserved
BDh
00h
Read/Write, Read Only
8 bits
Datasheet
Description
250687-002
R