RG82845M Intel, RG82845M Datasheet - Page 31

• Manufacturer Part Number: RG82845M
• Description: Chipset Memory Controller Hub Mobile
• Manufacturer: Intel

2.6.
2.7.
250687-002
Table 13. Voltage Reference Descriptions
R
This section describes the expected states of the MCH-M I/O buffers. These tables only refer to the
contributions on the interface from the MCH-M and do NOT reflect any external influence (such as
external pullup/pulldown resistors or external drivers).
Legend :
Term H/L: Normal termination devices are turned on high/low
Pwrdn:
H/L:
Tri/High-Z:
IN:
PU, PD/PL:
(Strap):
Voltage References, PLL Power
Pin State Table
HVREF
SDREF
HI_REF
AGPREF
HLRCOMP
GRCOMP
HRCOMP[1:0]
HSWNG[1:0]
SMRCOMP
VCC1_5
VCC1_8
VCCSM
VCCA[1:0]
VTT
VSS
VSSA[1:0]
Signal Name
CMOS
CMOS
CMOS
CMOS
CMOS
Power down
High Impedance
Input buffer Enabled
Weak internal pull-up, Weak internal pull down
Strap input sampled during assertion or on the deassertion edge of RSTIN#
Type
Strong Drive low
Ref
Ref
Ref
Ref
I/O
I/O
I/O
I/O
I
Host Reference Voltage. Reference voltage input for the Data, Address, and
Common clock signals of the Host AGTL+ interface
DDR Reference Voltage: Reference voltage input for DQ, DQS, & RCVENIN#.
Hub Interface Reference: Reference voltage input for the hub interface.
AGP Reference: Reference voltage input for the AGP interface.
Compensation for hub interface: This signal is used to calibrate the hub
interface I/O buffers.
Compensation for AGP: This signal is used to calibrate AGP buffers.
Compensation for Host: This signal is used to calibrate the Host AGTL+ I/O
buffers.
Host Reference Voltage: Reference voltage input for the compensation logic.
System Memory RCOMP
The 1.5 V Power input pins
The 1.8 V Power input pins
The SDRAM Power input pins. 2.5 V for DDR.
PLL power input pins.
The AGTL+ bus termination voltage inputs
GROUND
PLL Ground
Datasheet
Intel
®
82845MP/82845MZ Chipset-Mobile (MCH-M)
Description
31