RG82845M Intel, RG82845M Datasheet - Page 65

• Manufacturer Part Number: RG82845M
• Description: Chipset Memory Controller Hub Mobile
• Manufacturer: Intel

250687-002
Table 22. Control Signals for Various Memory Segments
R
At the time that a hub interface or AGP accesses to the PAM region may occur, the targeted PAM
segment must be programmed to be both readable and writeable.
As an example, consider BIOS that is implemented on the expansion bus. During the initialization
process, the BIOS can be shadowed in main memory to increase the system performance. When BIOS is
shadowed in main memory, it should be copied to the same address location. To shadow the BIOS, the
attributes for that address range should be set to write only. The BIOS is shadowed by first doing a read
of that address. This read is forwarded to the expansion bus. The host then does a write of the same
address, which is directed to main memory. After the BIOS is shadowed, the attributes for that memory
area are set to read only so that all writes are forwarded to the expansion bus. Figure 4 and Table 23
show the PAM registers and the associated attribute bits:
Bits [7, 3]
Reserved
X
X
X
X
Bits [6, 2]
Reserved
x
x
x
x
Bits [5, 1]
WE
0
0
1
1
Datasheet
Bits [4, 0]
RE
0
1
0
1
Intel
®
82845MP/82845MZ Chipset-Mobile (MCH-M)
Disabled. DRAM is disabled and all accesses are
directed to the hub interface A. The MCH-M does not
respond as a PCI target for any read or write access to
this area.
Read Only. Reads are forwarded to DRAM and writes
are forwarded to the hub interface A for termination.
This write protects the corresponding memory
segment. The MCH-M will respond as an AGP or the
hub interface A target for read accesses but not for
any write accesses.
Write Only. Writes are forwarded to DRAM and reads
are forwarded to the hub interface for termination. The
MCH-M will respond as an AGP or hub interface A
target for write accesses but not for any read
accesses.
Read/Write. This is the normal operating mode of
main memory. Both read and write cycles from the
host are claimed by the MCH-M and forwarded to
DRAM. The MCH-M will respond as an AGP or the
hub interface A target for both read and write
accesses.
Description
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