RG82845M Intel, RG82845M Datasheet - Page 63

• Manufacturer Part Number: RG82845M
• Description: Chipset Memory Controller Hub Mobile
• Manufacturer: Intel

3.7.19.
3.7.20.
250687-002
R
Address Offset:
Address Offset:
DERRSYN – DRAM Error Syndrome Register
Default Value:
Access:
Size:
This register is used to report the ECC syndromes for each quadword of a 32-Byte aligned data quantity
read from the DRAM array.
EAP – Error Address Pointer Register – Device #0
Default Value:
Access:
Size:
This register stores the DRAM address when an ECC error occurs.
7:0
31:30
29:1
Bit
Bit
0
Reserved
Error Address Pointer (EAP): This field is used to store the 4-KB block of main memory of which
an error (single bit or multi-bit error) has occurred.
Note: that the value of this bit field represents the address of the first single or the first multiple bit
error occurrence after the error flag bits in the ERRSTS register have been cleared by software. A
multiple bit error will overwrite a single bit error. Once the error flag bits are set as a result of an error,
this bit field is locked and doesn’t change as a result of a new error.
Reserved
DRAM ECC Syndrome (DECCSYN) (RO): After a DRAM ECC error, hardware loads this field with
a syndrome that describes the set of bits found to be in error.
Note: that this field is locked from the time that it is loaded up to the time when the error flag is
cleared by software. If the first error was a single bit, correctable error, then a subsequent multiple
bit error will overwrite this field. In all other cases, an error that occurs after the first error and
before the error flag has been cleared by software will escape recording.
86h
00hb
Read Only
8 bits
8C-8Fh
0000_0000h
Read Only
32 bits
Datasheet
Intel
®
Description
Description
82845MP/82845MZ Chipset-Mobile (MCH-M)
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