RG82845M Intel, RG82845M Datasheet - Page 143

• Manufacturer Part Number: RG82845M
• Description: Chipset Memory Controller Hub Mobile
• Manufacturer: Intel

9.4.
9.4.1.
250687-001
Figure 11. XOR–Tree Chain
R
Testability
In the MCH-M, testability for Automated Test Equipment (ATE) board level testing has been implemented
as and XOR chain. An XOR-tree is a chain of XOR gates, each with one input pin connected to it. Refer to
Figure 11 for an example XOR chain.
The algorithm used for in –circuit test is as follows
XOR Test Mode Initialization
XOR test mode can be entered by pulling three shared pins (reset straps) low through the rising transition
of RSTINB. The signals that need to be pulled are as follows:
GGNTB = 0 (Global strap enable)
SBA[1]
ST[2]
VCC1_8
• Drive all input pins to an initial logic level ‘1’. Observe the output corresponding to scan chain being
• Toggle pins one at a time starting from the first pin in the chain, continuing to the last pin, from its
tested.
initial logic level to the opposite logic level. Observe the output changes with each pin toggle.
Input
= 0 (XOR strap)
= 0 (PLL Bypass mode; it is recommended to enter PLL Bypass in XOR test mode)
Input
Input
Datasheet
Intel
®
Input
845MZ Chipset:82845MZ (MCH-M)
Input
xor.vsd
XOR
Out
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