S71PL032J SPANSION [SPANSION], S71PL032J Datasheet - Page 120

• Manufacturer Part Number: S71PL032J
• Description: STACKED MULTI CHIP PRODUCT FLASH MEMORY AND RAM
• Manufacturer: SPANSION [SPANSION]

Switching Waveforms
Notes:
1. To achieve 55-ns performance, the read access should be CE# controlled. In this case t
2. Device is continuously selected. OE#, CE# = V
3. WE# is High for Read Cycle.
Notes:
1. To achieve 55-ns performance, the read access should be CE# controlled. In this case t
2. WE# is High for Read Cycle.
120
DATA OUT
ADDRESS
BHE#/BLE#
satisfied when the addresses are stable prior to chip enable going active. For the 70-ns cycle, the addresses must be stable
within 10 ns after the start of the read cycle.
satisfied when the addresses are stable prior to chip enable going active. For the 70-ns cycle, the addresses must be stable
within 10 ns after the start of the read cycle.
DATA OUT
ADDRESS
CE#1
OE#
CE
2
PREVIOUS D ATA VALID
t
t
SK
SK
HIGH IMPEDENCE
Figure 44. Read Cycle 1 (Address Transition Controlled)
t
LZCE
t
LZBE
Figure 45. Read Cycle 2 (OE# Controlled)
t
t
ACE
LZOE
t OHA
t
t
DOE
DBE
A d v a n c e
IL
t AA
.
pSRAM Type 4
t
RC
t
RC
I n f o r m a t i o n
DATA VALID
ACE
ACE
t
is the critical parameter and t
is the critical parameter and t
HZOE
DATA VALID
t
HZBE
pSRAM_Type04_18A0 August 30, 2004
t
HZCE
IMPEDENCE
HIGH
SK
SK
is
is