S71PL032J SPANSION [SPANSION], S71PL032J Datasheet - Page 140

no-image

S71PL032J

Manufacturer Part Number
S71PL032J
Description
STACKED MULTI CHIP PRODUCT FLASH MEMORY AND RAM
Manufacturer
SPANSION [SPANSION]
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
S71PL032J04BAWOB
Manufacturer:
SPANSION
Quantity:
20 000
Part Number:
S71PL032J04BFWOP
Manufacturer:
SPANSION
Quantity:
5 792
Part Number:
S71PL032J08BFW0B
Manufacturer:
SPANSION
Quantity:
20 000
Part Number:
S71PL032J40BAW0K
Manufacturer:
SPANSION
Quantity:
20 000
Part Number:
S71PL032J40BAWOK0
Manufacturer:
SPANSION
Quantity:
10 882
Part Number:
S71PL032J40BFWOB
Manufacturer:
SPANSION
Quantity:
5 795
Part Number:
S71PL032J40BFWOK0
Manufacturer:
SPANSION
Quantity:
10 888
Part Number:
S71PL032J70BF112
Manufacturer:
SPANSION
Quantity:
5 799
Part Number:
S71PL032JA0BFWQF0
Manufacturer:
SPANSION
Quantity:
20 000
AC Characteristics
Notes:
1. Maximum value is applicable if CE1# is kept at Low without any address change. If the relaxation is needed by system
2. Minimum value must be equal or greater than the sum of write pulse (t
3. Write pulse is defined from High to Low transition of CE1#, WE#, or LB#/UB#, whichever occurs last.
4. Applicable for byte mask only. Byte mask setup time is defined to the High to Low transition of CE1# or WE# whichever
5. Applicable for byte mask only. Byte mask hold time is defined from the Low to High transition of CE1# or WE# whichever
6. Write recovery is defined from Low to High transition of CE1#, WE#, or LB#/UB#, whichever occurs first.
7. t
8. If OE# is Low after minimum t
9. If OE# is Low after new address input, read cycle is initiated. In other word, OE# must be brought to High at the same time
140
Write Cycle Time
Address Setup Time
CE1# Write Pulse Width
WE# Write Pulse Width
LB#/UB# Write Pulse Width
LB#/UB# Byte Mask Setup Time
LB#/UB# Byte Mask Hold Time
Write Recovery Time
CE1# High Pulse Width
WE# High Pulse Width
LB#/UB# High Pulse Width
Data Setup Time
Data Hold Time
OE# High to CE1# Low Setup Time for Write
OE# High to Address Setup Time for Write
LB# and UB# Write Pulse Overlap
operation, please contact local Spansion representative for the relaxation of 1µs limitation.
occurs last.
occurs first.
CE1# is brought to Low. Once read cycle is initiated, new write pulse should be input after minimum t
or before new address valid. Once read cycle is initiated, new write pulse should be input after minimum t
bus is in High-Z.
WPH
minimum is absolute minimum value for device to detect High level. And it is defined at minimum V
Write Operation
Parameter
OHCL
, read cycle is initiated. In other words, OE# must be brought to High within 5ns after
Symbol
A d v a n c e
t
t
t
t
t
OHCL
t
t
t
t
t
t
t
t
t
t
WHP
t
BWO
BHP
OES
WC
CW
BW
WR
WP
BH
DS
DH
AS
BS
CP
pSRAM Type 7
Min.
7.5
70
45
45
45
10
10
15
30
-5
-5
-5
0
0
0
0
16M
Max.
1000
1000
1000
I n f o r m a t i o n
CW
Min.
, t
7.5
65
40
40
40
–5
–5
12
12
12
–5
30
0
0
0
0
WP
32M
or t
Max.
1000
1000
1000
BW
) and write recovery time (t
Min.
7.5
65
40
40
40
–5
–5
12
12
12
–5
30
0
0
0
0
pSRAM_Type07_13_A1 November 2, 2004
64M
Max.
1000
1000
1000
RC
is met.
IH
RC
level.
is met and data
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WR
).
Notes
1,2
3
3
3
3
4
5
6
7
8
9

Related parts for S71PL032J