S71PL032J SPANSION [SPANSION], S71PL032J Datasheet - Page 7

• Manufacturer Part Number: S71PL032J
• Description: STACKED MULTI CHIP PRODUCT FLASH MEMORY AND RAM
• Manufacturer: SPANSION [SPANSION]

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Functional Description . . . . . . . . . . . . . . . . . . . . 164
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 164
Timing Test Conditions . . . . . . . . . . . . . . . . . . . 170
Power Up Sequence . . . . . . . . . . . . . . . . . . . . . . . 171
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 183
November 22, 2004 S71PL254/127/064/032J_00_A6
Output Load Circuit ......................................................................................... 171
Read Cycle .......................................................................................................... 183
is Low, Ignore UB#/LB# Timing) ........................................ 161
Figure 82. Timing Waveform of Write Cycle(1) (WE# controlled, if
BYTE# is Low, Ignore UB#/LB# Timing).............................. 161
Figure 83. Timing Waveform of Write Cycle(2) (CS# controlled, if
BYTE# is Low, Ignore UB#/LB# Timing).............................. 162
Figure 84. Timing Waveform of Write Cycle(3) (UB#, LB#
controlled) ...................................................................... 162
Figure 85. Data Retention Waveform .................................. 163
Figure 86. Output Load Circuit ........................................... 171
Figure 87. Timing of Read Cycle (CE# = OE# = V
V
IH
)................................................................................ 183
pSRAM Type 1
A d v a n c e
IL
, WE# = ZZ# =
I n f o r m a t i o n
Write Cycle .........................................................................................................186
Partial Array Self Refresh (PAR) .................................................................. 188
Temperature Compensated Refresh (for 64Mb) ................................... 188
Deep Sleep Mode ............................................................................................. 188
Reduced Memory Size (for 32M and 16M) ................................................ 188
Other Mode Register Settings (for 64M) ...................................................189
Figure 88. Timing Waveform of Read
Cycle (WE# = ZZ# = V
Figure 89. Timing Waveform of Page Mode Read Cycle (WE# = ZZ#
= V
Figure 90. Timing Waveform of Write Cycle (WE# Control, ZZ# =
V
Figure 91. Timing Waveform of Write Cycle (CE# Control, ZZ# =
V
Figure 92. Timing Waveform of Page Mode Write Cycle (ZZ# = V
187
Figure 93. Mode Register .................................................. 189
Figure 94. Mode Register Update Timings (UB#, LB#, OE# are
Don’t Care)..................................................................... 190
Figure 95. Deep Sleep Mode - Entry/Exit Timings................. 190
IH
IH
) ............................................................................... 186
) ............................................................................... 186
IH
)............................................................................ 185
Revision Summary
IH
) ................................................ 184
IH
7
)