S71PL032J SPANSION [SPANSION], S71PL032J Datasheet - Page 189

• Manufacturer Part Number: S71PL032J
• Description: STACKED MULTI CHIP PRODUCT FLASH MEMORY AND RAM
• Manufacturer: SPANSION [SPANSION]

June 8, 2004 pSRAM_Type01_12_A0
Other Mode Register Settings (for 64M)
Must set to all 0
A21 - A8
Reserved
0 = Page Mode Disabled (default)
1 = Page Mode Enabled
transitioning high and the mode remains active until the register is updated. To
return to the full 32Mb address space, the VA register must be reset using the
previously defined procedures. While operating in the RMS mode, the unselected
portion of the array may not be used.
The Page Mode operation can also be enabled and disabled using the Mode Reg-
ister. Register bit A7 controls the operation of Page Mode and setting this bit to a
one (1), enables Page Mode. If the register bit A7 is set to a zero (0), Page Mode
operation is disabled.
Page Mode
A7
A d v a n c e
1
0
0
1
A6
64 Mb
Compensated
0 = 15
1 = 45
0 = 70
1 = 85
Refresh
Temp
Figure 93. Mode Register
o
o
o
o
I n f o r m a t i o n
C
C
C
C (default)
0 = Deep Sleep Enabled
1 = Deep Sleep Disabled (default)
A5
Deep Sleep Enable/Disable
pSRAM Type 1
A4
32 Mb / 16 Mb
Array Mode
0 = PAR (default)
1 = RMS
for ZZ#
A3
1
1
1
1
0
0
0
0
A2
1
1
0
0
1
1
0
0
1 = Top 1/4 array
0 = Top 1/2 array
1 = Top 3/4 array
0 = No PAR
1 = Bottom 1/4 array
0 = Bottom 1/2 array
1 = Bottom 3/4 array
0 = Full array (default)
PAR Section
A1
A0
189