S3C72G9 Samsung semiconductor, S3C72G9 Datasheet - Page 25

• Manufacturer Part Number: S3C72G9
• Description: The S3C72G9 single-chip CMOS microcontroller has been designed for high performance using Samsungs newest 4-bit CPU core/ SAM47 (Samsung Arrangeable M
• Manufacturer: Samsung semiconductor

 

ADC
Operation:
Description:
Examples:
dst,src
A,@HL
EA,RR
RRb,EA
The source operand, along with the setting of the carry flag, is added to the destination operand
and the sum is stored in the destination. The contents of the source are unaffected. If there is an
overflow from the most significant bit of the result, the carry flag is set; otherwise, the carry flag is
cleared.
If 'ADC A,@HL' is followed by an 'ADS A,#im' instruction in a program, ADC skips the ADS
instruction if an overflow occurs. If there is no overflow, the ADS instruction is executed normally.
(This condition is valid only for 'ADC A,@HL' instructions. If an overflow occurs following an 'ADS
A,#im' instruction, the next instruction will not be skipped.)
A,@HL
EA,RR
RRb,EA
1. The extended accumulator contains the value 0C3H, register pair HL the value 0AAH, and
2. If the extended accumulator contains the value 0C3H, register pair HL the value 0AAH, and
Operand
Operand
the carry flag is set to "1":
SCF
ADC
JPS
the carry flag is cleared to "0":
RCF
ADC
JPS

Add indirect data memory to A with carry
Add register pair (RR) to EA with carry
Add EA to register pair (RRb) with carry
EA,HL
XXX
EA,HL
XXX
0
1
1
1
1
0
1
0
1
0
1
0
1
0
1
Binary Code
Operation Summary
1
1
0
1
0
; C
; EA
; Jump to XXX;no skip after ADC
; C
; EA
; Jump to XXX; no skip after ADC
1
1
1
1
0
r2
r2
1
1
1
"1"
"0"
0C3H + 0AAH + 1H = 6EH, C
0C3H + 0AAH + 0H = 6DH, C
r1
r1
1
0
0
0
0
0
0
0
C, A
C, EA
C, RRb
A + (HL) + C
Operation Notation
EA + RR + C
RRb + EA + C

 


Bytes
1
2
2
"1"
"1"
Cycles
1
2
2