S3C72G9 Samsung semiconductor, S3C72G9 Datasheet - Page 73
S3C72G9
Manufacturer Part Number
S3C72G9
Description
The S3C72G9 single-chip CMOS microcontroller has been designed for high performance using Samsungs newest 4-bit CPU core/ SAM47 (Samsung Arrangeable M
Manufacturer
Samsung semiconductor
Datasheet
1.S3C72G9.pdf
(96 pages)
- Current page: 73 of 96
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NOP
Operation:
Description:
Example:
No operation is performed by a NOP instruction. It is typically used for timing delays.
One NOP causes a 1-cycle delay: with a 1 µs cycle time, five NOPs would therefore cause a 5 µs
delay. Program execution continues with the instruction immediately following the NOP. Only the
PC is affected. At least three NOP instructions should follow a STOP or IDLE instruction.
Three NOP instructions follow the STOP instruction to provide a short interval for clock
stabilization before power-down mode is initiated:
STOP
NOP
NOP
NOP
Operand
Operand
–
–
No operation
1
0
1
Binary Code
Operation Summary
0
0
0
0
0
No operation
Operation Notation
Bytes
1
Cycles
1
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