S3C72G9 Samsung semiconductor, S3C72G9 Datasheet - Page 95

• Manufacturer Part Number: S3C72G9
• Description: The S3C72G9 single-chip CMOS microcontroller has been designed for high performance using Samsungs newest 4-bit CPU core/ SAM47 (Samsung Arrangeable M
• Manufacturer: Samsung semiconductor

 
 
XCHI
Operation:
Description:
Example:
dst,src
A,@HL
The instruction XCHI exchanges the contents of the accumulator with the RAM location addressed
by register pair HL and then increments the contents of register L. If the content of register L is 0H,
a skip is executed. The value of the carry flag is unaffected.
A,@HL
Register pair HL contains the address 2FH and internal RAM location 2FH contains 0FH:
YYY
The 'JPS YYY' instruction is executed since a skip occurs after the XCHI instruction.
Operand
Operand
LD
LD
XCHI
JPS
JPS
XCHI



Exchange A and data memory contents; increment
contents of register L and skip on overflow
0
1
HL,#2FH
A,#0H
A,@HL
XXX
YYY
A,@HL
1

Binary Code
Operation Summary
1
; A
; Skipped since an overflow occurred
; H
; (20H)
1
0
0FH and L
2H, L
0FH, A
1
0
0H
L + 1 = 0, (HL)
A
skip if L = 0H
(20H), L
(HL), then L
Operation Notation
L + 1 = 1H

 


Bytes
1
"0"
L+1;
Cycles
2 + S