S3C72G9 Samsung semiconductor, S3C72G9 Datasheet - Page 90

• Manufacturer Part Number: S3C72G9
• Description: The S3C72G9 single-chip CMOS microcontroller has been designed for high performance using Samsungs newest 4-bit CPU core/ SAM47 (Samsung Arrangeable M
• Manufacturer: Samsung semiconductor

 


 
STOP
Operation:
Description:
Example:

The STOP instruction stops the system clock by setting bit 3 of the power control register (PCON)
to logic one. When STOP executes, all system operations are halted with the exception of some
peripheral hardware with special power-down mode operating conditions.
In application programs, a STOP instruction must be immediately followed by at least three NOP
instructions. This ensures an adequate time interval for the clock to stabilize before the next
instruction is executed. If three or more NOP instructions are not used after STOP instruction,
leakage current could be flown because of the floating state in the internal bus.
Given that bit 3 of the PCON register is cleared to logic zero, and all systems are operational, the
instruction sequence
STOP
NOP
NOP
NOP
sets bit 3 of the PCON register to logic one, stopping all controller operations (with the exception
of some peripheral hardware). The three NOP instructions provide the necessary timing delay for
clock stabilization before the next instruction in the program sequence is executed.
Operand
Operand
–
–
Engage CPU stop mode
1
1


1
0
1
1
Binary Code
Operation Summary
1
1
1
0
1
0
1
1
1
1
PCON.3
Operation Notation
1
Bytes
2

 
Cycles
2