S3C72G9 Samsung semiconductor, S3C72G9 Datasheet - Page 27
S3C72G9
Manufacturer Part Number
S3C72G9
Description
The S3C72G9 single-chip CMOS microcontroller has been designed for high performance using Samsungs newest 4-bit CPU core/ SAM47 (Samsung Arrangeable M
Manufacturer
Samsung semiconductor
Datasheet
1.S3C72G9.pdf
(96 pages)
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ADS
Description:
Examples:
Operation:
dst,src
A, #im
EA, #imm
A,@HL
EA,RR
RRb, EA
The source operand is added to the destination operand and the sum is stored in the destination.
The contents of the source are unaffected. If there is an overflow from the most significant bit of
the result, the skip signal is generated and a skip is executed, but the carry flag value is
unaffected.
If 'ADS A,#im' follows an 'ADC A,@HL' instruction in a program, ADC skips the ADS instruction if
an overflow occurs. If there is no overflow, the ADS instruction is executed normally. This skip
condition is valid only for 'ADC A,@HL' instructions, however. If an overflow occurs following an
ADS instruction, the next instruction is not skipped.
A, #im
EA,#imm
A,@HL
EA,RR
RRb,EA
1. The extended accumulator contains the value 0C3H, register pair HL the value 0AAH, and
Operand
Operand
the carry flag = "0":
ADS
JPS
JPS
Add 4-bit immediate data to A and skip on overflow
Add 8-bit immediate data to EA and skip on overflow
Add indirect data memory to A and skip on overflow
Add register pair (RR) contents to EA and skip on
overflow
Add EA to register pair (RRb) and skip on overflow
EA,HL
XXX
YYY
d7
1
1
0
1
1
1
1
d6
0
1
0
1
0
1
0
d5
1
0
1
0
0
0
0
Binary Code
Operation Summary
d4
0
0
1
1
1
1
1
; This instruction is skipped since ADS had an overflow.
; EA
; ADS skips on overflow, but carry flag value is not
; affected.
; Jump to YYY.
d3
d3
1
1
1
1
1
0
d2
d2
r2
r2
1
1
1
0
0C3H + 0AAH = 6DH
d1
d1
r1
r1
0
1
0
0
d0
d0
1
1
0
0
0
0
A
EA
A
EA
RRb
A + im; skip on overflow
A + (HL); skip on overflow
EA + imm; skip on overflow
EA + RR; skip on overflow
Operation Notation
RRb + EA; skip on overflow
Bytes
1
1
2
2
2
Cycles
1 + S
2 + S
1 + S
2 + S
2 + S
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