S3C72G9 Samsung semiconductor, S3C72G9 Datasheet - Page 52

• Manufacturer Part Number: S3C72G9
• Description: The S3C72G9 single-chip CMOS microcontroller has been designed for high performance using Samsungs newest 4-bit CPU core/ SAM47 (Samsung Arrangeable M
• Manufacturer: Samsung semiconductor

 



DI
Operation:
Description:
Example:

Bit 3 of the interrupt priority register IPR, IME, is cleared to logic zero, disabling all interrupts.
Interrupts can still set their respective interrupt status latches, but the CPU will not directly service
them.
If the IME bit (bit 3 of the IPR) is logic one (e.g., all instructions are enabled), the instruction
DI
sets the IME bit to logic zero, disabling all interrupts.
Operand
Operand
-
-

Disable all interrupts
1
1
1
0
1
1
Binary Code
Operation Summary
1
1
1
0
1
0
1
1
0
0
IME
0
Operation Notation
Bytes
2

 
Cycles
2