S3C72G9 Samsung semiconductor, S3C72G9 Datasheet - Page 58

• Manufacturer Part Number: S3C72G9
• Description: The S3C72G9 single-chip CMOS microcontroller has been designed for high performance using Samsungs newest 4-bit CPU core/ SAM47 (Samsung Arrangeable M
• Manufacturer: Samsung semiconductor

 



JPS
Operation:
Description:
Example:



dst
ADR
JPS causes an unconditional branch to the indicated address with the 4 K byte program memory
address space. Bits 0-11 of the program counter are replaced with the directly specified address.
The destination address for this jump is specified to the assembler by a label or by an actual
address in program memory.
ADR
The label 'SUB' is assigned to the instruction at program memory location 00FFH. The instruction
JPS
at location 0EABH will load the program counter with the value 00FFH. Normally, the JPS
instruction jumps to the address in the block in which the instruction is located. If the first byte of
the instruction code is located at address xFFEH or xFFFH, the instruction will jump to the next
block. If the instruction 'JPS SUB' were located instead at program memory address 0FFEH or
0FFFH, the instruction 'JPS SUB' would load the PC with the value 10FFH, causing a program
malfunction.
Operand
Operand
SUB


Jump direct in page (12 bits)
a7
1
a6
0
a5
0
Binary Code
Operation Summary
a4
1
a11 a10
a3
a2
a9
a1
a8
a0
PC14-0
Operation Notation
PC14-12+ADR11-0
Bytes
2

 
Cycles
2