VT8601 Via, VT8601 Datasheet - Page 100

• Manufacturer Part Number: VT8601
• Description: Slot-1 / Socket-370 PCI North Bridge
• Manufacturer: Via

CR38 – Pixel Bus Mode .................................................... RW
This register is protected by SRE_New[7]
CR39 – PCI Interface Control ......................................... RW
This register is protected by SRE_New[7]
Revision 1.3 September 8, 1999
7-6
6-5
4-3
5
4
3
2
1
0
7
2
1
0
7HFKQRORJLHV ,QF
Reserved
Packed 24-Bit True-Color Mode
Standard VGA Mode in 64-Bit Configuration
True Color Mode
High Color Mode
Reserved
16-Bit Pixel Bus
Pixel Data Format
Memory Data with Big Endian Format
BE[3-0]# With Big Endian Format
PCI Burst Write
PCI Burst Read
MMIO Control.....default set from Inverted MA??
:H &
:H &R R QQHFW
00 Pass Through (PT) .................................default
01 Word Swap (WS)
10 Half Swap (HS)
11 Full Swap (FS)
00 Pass Through (PT) .................................default
01 Word Swap (WS)
10 Half Swap (HS)
11 Full Swap (FS)
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
QQHFW
Disable ...................................................default
Enable
Disable ...................................................default
Enable
Disable ...................................................default
Enable
Disable ...................................................default
Enable
Disable ...................................................default
Enable
Little Endian...........................................default
Big Endian
Disable ...................................................default
Enable
Disable ...................................................default
Enable
Disable
Enable (64KB VGA I/O space can be memory
mapped within the 4GB memory space)
........................................ always reads 0
........................................ always reads 0
-94
CR3A – Physical Address Control .................................. RW
CR3B – Clock and Tuning ............................................... RW
This register is protected by SRE_New[7]
CR3C – Miscellaneous Control ....................................... RW
This register is protected by SRE_New[7]
6-4
2-1
7-3
7
6
5
4
3
2
1
0
7
3
0
2
1
0
Reserved
AGP / PCI Select
Both IO
Memory Address Linearization
Reserved
AGP Software Reset
PCI Configuration Subsystem ID Write
Enhanced Register I/O Scheme
Observe Clock Source
Clock Source Mode Select
Bit 6 default is set from MA?? inverted
Bits 5-4 default to 00
Clock Control
Reserved
Vertical Retrace Memory Refresh
Same Definition as GRF[7-3]................... default = 0
Reserved
Same Definition as GRF[1] ...................... default = 0
Mode Select 1............................................ default = 0
0xx Internal Clock Chip
1xx External Clock Chip
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
PCI
AGP
Disable................................................... default
Enable
Disable................................................... default
Enable
Normal................................................... default
Reset
Disable................................................... default
Enable
Disable................................................... default
Enable
VCLK1 .................................................. default
VCLK2
000 V/MCLK test mode, observe MCLK
001 V/MCLK test mode, observe VCLK1
010 V/MCLK test mode, observe VCLK2
011 Normal operation
When bits 6-4 = 00x, clock is normal.... default
When bits 6-4 = 00x, clock is divided by 2
Disable
Enable................................................... default
This register has no function.................. default
The original GRF[7-0] bits are used
GRF[7-3, 1] accessed via this register only
GRF[2, 0] accessed at original register only
Original GRF[3] is R/W but has no function
........................................ always reads 0
.................................................... default
........................................ always reads 0
........................................ always reads 0
........................................ always reads 0
VT8601 Apollo ProMedia
VGA Extended Registers