VT8601 Via, VT8601 Datasheet - Page 60

• Manufacturer Part Number: VT8601
• Description: Slot-1 / Socket-370 PCI North Bridge
• Manufacturer: Via

Device 1 Bus 0 PCI-to-AGP Bridge Registers
AGP Bus Control
Device 1 Offset 40 - CPU-to-AGP Flow Control 1 ......... RW
Revision 1.3 September 8, 1999
3E[3]
VGA
Pres.
7
6
5
4
3
2
1
0
Table 5. VGA/MDA Memory/IO Redirection
0
1
1
7HFKQRORJLHV ,QF
CPU-AGP Post Write
CPU-AGP Dynamic Burst
CPU-AGP One Wait State Burst Write
AGP to DRAM Prefetch
AGP Master Allowed Before CPU-to-AGP Post
Write Buffer is Not Flushed
This option is always enabled for PCI
MDA Present on AGP
Note: Forward despite IO / Memory Base / Limit
Note:
addresses are memory addresses B0000h-B7FFFh
and I/O addresses 3B4-3B5h, 3B8-3BAh, and 3BFh
(10-bit decode). 3BC-3BE are reserved for printers.
Note: If Rx3E bit-3 is 0, this bit is a don't care (MDA
accesses are forwarded to the PCI bus).
AGP Master Read Caching
AGP Delay Transaction
:H &
:H &R R QQHFW
MDA
40[2]
Pres.
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
-
QQHFW
Disable ...................................................default
Enable
Disable ...................................................default
Enable
Disable ...................................................default
Enable
Disable ...................................................default
Enable
Disable ...................................................default
Enable
Forward MDA accesses to AGP.............default
Forward MDA accesses to PCI
Disable ...................................................default
Enable
Disable ...................................................default
Enable
VGA
AGP AGP
AGP PCI
PCI
on
is
MDA (Monochrome Display Adapter)
MDA
PCI
on
is
Axxxx,
Access
B8xxx
AGP
AGP
PCI
-B7FFF
Access
B0000
AGP AGP AGP
PCI
PCI
AGP PCI
3Cx,
3Dx
PCI
I/O
3Bx
PCI
I/O
-54-
Device 1 Offset 41 - CPU-to-AGP Flow Control 2 ...... RWC
Device 1 Offset 42 - AGP Master Control ...................... RW
5-4
1-0
7
6
3
2
7
6
5
4
3
2
1
0
Retry Status
Retry Timeout Action
Retry Count
Post Write Data on Abort
CPU Backoff on AGP Read Retry Timeout
Reserved
Read Prefetch for Enhance Command
AGP Master One Wait State Write
AGP Master One Wait State Read
Extend AGP Internal Master for Efficient
Handling of Dummy Request Cycles
This bit is normally set to 1.
AGP Delay Transaction Timeout
Prefetch During Delay Transaction
Reserved
Reserved (do not use) ...............................default = 0
00 Retry 2, backoff CPU ............................ default
01 Retry 4, backoff CPU
10 Retry 16, backoff CPU
11 Retry 64, backoff CPU
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
No retry occurred................................... default
Retry Occurred ........................write 1 to clear
No action taken except to record status ....... def
Flush buffer for write or return all 1s for read
Flush entire post-write buffer on target-abort
or master abort ....................................... default
Pop one data output on target-abort or master-
abort
Disable................................................... default
Enable
Always Perform Prefetch ....................... default
Prefetch only if Enhance Command
Disable................................................... default
Enable
Disable................................................... default
Enable
Disable................................................... default
Enable
Disable................................................... default
Enable
Enable .................................................... default
Disable
Device 1 Bus 0 PCI-to-AGP Bridge Registers
........................................always reads 0
........................................always reads 0
VT8601 Apollo ProMedia